coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mt6363_read8 API
by Yu-Ping Wu (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85892?usp=email ) Change subject: soc/mediatek/mt8196: Add mt6363_read8 API ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cca4c2e5f6c2537c9661623260b21fb6088eff9 Gerrit-Change-Number: 85892 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 14:13:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/84672?usp=email ) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... Patch Set 9: (2 comments) This change is ready for review. File src/mainboard/asrock/z87_extreme4/Kconfig: https://review.coreboot.org/c/coreboot/+/84672/comment/8264658a_c7d3f5dd?us… : PS1, Line 28: config USBDEBUG_HCD_INDEX # FIXME: check this : int : default 2 > Let's leave it as-is. Both debug ports are now accounted for. File src/mainboard/asrock/z87_extreme4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84672/comment/ac4170e2_eed5e982?us… : PS1, Line 54: device pci 1c.0 on # PCIe Port #1 : subsystemid 0x1849 0x8c10 : end : device pci 1c.1 on # PCIe Port #2 : end : device pci 1c.2 on # PCIe Port #3 : subsystemid 0x1849 0x8c14 : end : device pci 1c.3 on # RP #4: PCIe x1 slot : end : device pci 1c.4 on # PCIe Port #5 : end : device pci 1c.5 on # PCIe Port #6 : end : device pci 1c.6 on # PCIe Port #7 : end : device pci 1c.7 on # PCIe Port #8 : end > Have a look at the PCIe RPs now. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 9 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 14:04:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Philipp Groß <jeangrande(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: lint/checkpatch: Add __aligned to the list of attribute notes
by Elyes Haouas (Code Review) 10 Jan '25

10 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81949?usp=email ) Change subject: lint/checkpatch: Add __aligned to the list of attribute notes ...................................................................... lint/checkpatch: Add __aligned to the list of attribute notes This updates the script to upstream version 6.8 https://github.com/torvalds/linux/commit/2f9dadba5ba02e1510a04ce57ebfb9e08f… Change-Id: I9274e8b5ed5ada27c290c462b0c59eccf1b0b60d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81949 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/lint/checkpatch.pl 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index b6ac890..16b6bd3 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -517,6 +517,7 @@ __ro_after_init| __kprobes| $InitAttribute| + __aligned\s*$.*$| ____cacheline_aligned| ____cacheline_aligned_in_smp| ____cacheline_internodealigned_in_smp| -- To view, visit https://review.coreboot.org/c/coreboot/+/81949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9274e8b5ed5ada27c290c462b0c59eccf1b0b60d Gerrit-Change-Number: 81949 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85632?usp=email ) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... Patch Set 11: (1 comment) File src/drivers/amd/opensil/mpio/chip.h: https://review.coreboot.org/c/coreboot/+/85632/comment/5cf7f2f5_46ab68b1?us… : PS11, Line 6: #if CONFIG(OPENSIL_DRIVER) hmm, why is this needed to get rid of this build error for the EMULATION_QEMU_X86_Q35 config which shouldn't be including this file? In file included from src/drivers/amd/opensil/mpio/chip.c:6: src/drivers/amd/opensil/mpio/chip.h:6:10: error: #include expects "FILENAME" or <FILENAME> 6 | #include CONFIG_AMD_OPENSIL_MPIO_CHIP_H_FILE | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ i don't see the need for this guard, but i really wonder why the compiler's preprocessor tries to process this file in the EMULATION_QEMU_X86_Q35 case which doesn't select OPENSIL_DRIVER -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 11 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 13:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/common/psp_gen2: Add config for PSP MBOX offset
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85626?usp=email ) Change subject: soc/amd/common/psp_gen2: Add config for PSP MBOX offset ...................................................................... soc/amd/common/psp_gen2: Add config for PSP MBOX offset Some SoC like Glinda use different PSP MBOX offset. Add config to allow SoC Kconfig to override PSP MBOX offset. Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85626 Reviewed-by: Ana Carolina Cabral Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 6 insertions(+), 2 deletions(-) Approvals: Felix Held: Looks good to me, approved Ana Carolina Cabral: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 07ee0fa..17853fa 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -202,3 +202,7 @@ default y if SOC_AMD_COMMON_BLOCK_PSP help Select this if AMDFWTOOL needs to be built + +config PSPV2_MBOX_CMD_OFFSET + hex + default 0x10570 diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 21c1f2a..026d32f 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -8,8 +8,8 @@ #include <device/mmio.h> #include "psp_def.h" -#define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ -#define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ +#define PSP_MAILBOX_COMMAND_OFFSET CONFIG_PSPV2_MBOX_CMD_OFFSET /* 4 bytes */ +#define PSP_MAILBOX_BUFFER_OFFSET (CONFIG_PSPV2_MBOX_CMD_OFFSET + 4) /* 8 bytes */ #define IOHC_MISC_PSP_MMIO_REG 0x2e0 -- To view, visit https://review.coreboot.org/c/coreboot/+/85626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211 Gerrit-Change-Number: 85626 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85749?usp=email ) Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC 1) Initial commit for crater mainboard changes for RN/CZ SOC 2) Add the initial DXIO descriptors for crater 3) Add the DDI descriptors for crater 4) GPIO changes for crater mainboard TEST:Build crater mainboard changes with cezanne SOC Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/mainboard/amd/crater/Kconfig A src/mainboard/amd/crater/Kconfig.name A src/mainboard/amd/crater/Makefile.mk A src/mainboard/amd/crater/board_info.txt A src/mainboard/amd/crater/board_renoir.fmd A src/mainboard/amd/crater/bootblock.c A src/mainboard/amd/crater/chromeos.c A src/mainboard/amd/crater/chromeos_renoir.fmd A src/mainboard/amd/crater/devicetree_renoir.cb A src/mainboard/amd/crater/dsdt.asl A src/mainboard/amd/crater/early_gpio.c A src/mainboard/amd/crater/ec.c A src/mainboard/amd/crater/ec.h A src/mainboard/amd/crater/gpio.c A src/mainboard/amd/crater/gpio.h A src/mainboard/amd/crater/mainboard.c A src/mainboard/amd/crater/port_descriptors_renoir.c 17 files changed, 909 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig new file mode 100644 index 0000000..61b8f3e --- /dev/null +++ b/src/mainboard/amd/crater/Kconfig @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_AMD_CRATER_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM + select EC_ACPI + select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE + select MAINBOARD_HAS_CHROMEOS + select HAVE_ACPI_RESUME + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + select SOC_AMD_COMMON_BLOCK_PSP_RPMC + select SOC_AMD_COMMON_BLOCK_PSP_SMI + +config BOARD_AMD_CRATER_RENOIR + select BOARD_AMD_CRATER_COMMON + select SOC_AMD_CEZANNE + +if BOARD_AMD_CRATER_RENOIR + +config FMDFILE + default "src/mainboard/amd/crater/chromeos_renoir.fmd" if CHROMEOS + default "src/mainboard/amd/crater/board_renoir.fmd" + +config MAINBOARD_DIR + default "amd/crater" + +config MAINBOARD_PART_NUMBER + default "Crater_RENOIR" + +config DEVICETREE + default "devicetree_renoir.cb" + +config CRATER_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config CRATER_MCHP_SIG_FILE + string "Microchip EC signature file" + depends on CRATER_HAVE_MCHP_FW + help + The EC sig blob is the first 4kBytes of the firmware image. + The first 4 bytes form a pointer (with CRC) to where the EC firmware + is located + +config AMD_SOC_CONSOLE_UART + default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + +config CRATER_MCHP_FW_FILE + string "Microchip EC firmware file" + depends on CRATER_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/crater/EcSig_Crater.bin" + help + The EC firmware blob is at the EC_BODY FMAP region of the firmware image. + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + # Add the EFS and EC to the RO region only + # This is a crater specific override of soc/amd/cezanne/Kconfig + default "apu/amdfw apu/ecfw" + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + # We don't have recovery buttons, so we can't manually enable devmode. + select GBB_FLAG_FORCE_DEV_SWITCH_ON + +config ENABLE_EDP + bool "Enable EDP display" + default n + help + Select this option to enable EDP display on DDI1 interface + +config ENABLE_EVAL_CARD + bool "Enable Eval Card" + help + Enable the Eval Card PCIe slot + +config ENABLE_EVAL_19V + bool "Enable 19V rail for Eval Card" + depends on ENABLE_EVAL_CARD + help + Enable the 19V rail for Eval Card PCIe slot + +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig +config EFS_SPI_READ_MODE + default 3 # Quad IO (1-1-4) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config EFS_SPI_MICRON_FLAG + default 0 + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 1 # 33MHz + +config TPM_SPI_SPEED + default 1 # 33MHz + +endif # !EM100 + +endif # BOARD_AMD_CRATER_COMMON diff --git a/src/mainboard/amd/crater/Kconfig.name b/src/mainboard/amd/crater/Kconfig.name new file mode 100644 index 0000000..e49afa5 --- /dev/null +++ b/src/mainboard/amd/crater/Kconfig.name @@ -0,0 +1,4 @@ +comment "Crater" + +config BOARD_AMD_CRATER_RENOIR + bool "-> Crater for Renoir SoC" diff --git a/src/mainboard/amd/crater/Makefile.mk b/src/mainboard/amd/crater/Makefile.mk new file mode 100644 index 0000000..dc169f1 --- /dev/null +++ b/src/mainboard/amd/crater/Makefile.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c +bootblock-y += ec.c + +romstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c + +ramstage-y += chromeos.c +ramstage-y += gpio.c +ramstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c + +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin),) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_DefaultRecovery.bin +else +show_notices:: warn_no_apcb +endif + +ifeq ($(CONFIG_CRATER_HAVE_MCHP_FW),y) +$(call add_intermediate, add_mchp_fw) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_CRATER_MCHP_SIG_FILE) --fill-upward + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_CRATER_MCHP_FW_FILE) --fill-upward + +else +show_notices:: warn_no_mchp +endif + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the EC FW.\n" + printf "Do not flash this image. Your Crater's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/crater/board_info.txt b/src/mainboard/amd/crater/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/crater/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/crater/board_renoir.fmd b/src/mainboard/amd/crater/board_renoir.fmd new file mode 100644 index 0000000..556e295 --- /dev/null +++ b/src/mainboard/amd/crater/board_renoir.fmd @@ -0,0 +1,11 @@ +FLASH@0xFF000000 16M { + BIOS { + EC_SIG 4K + FMAP 4K + COREBOOT(CBFS) + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K + EC_BODY@15872K 256K + RW_MRC_CACHE 64K + } +} diff --git a/src/mainboard/amd/crater/bootblock.c b/src/mainboard/amd/crater/bootblock.c new file mode 100644 index 0000000..58ef0ba --- /dev/null +++ b/src/mainboard/amd/crater/bootblock.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/espi.h> +#include "ec.h" +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + espi_switch_to_spi2_pads(); +} + +void bootblock_mainboard_init(void) +{ + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD)) + crater_ec_init(); +} diff --git a/src/mainboard/amd/crater/chromeos.c b/src/mainboard/amd/crater/chromeos.c new file mode 100644 index 0000000..d5dc96c --- /dev/null +++ b/src/mainboard/amd/crater/chromeos.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = {}; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Crater doesn't have a write protect pin */ + return 0; +} + +DECLARE_NO_CROS_GPIOS(); diff --git a/src/mainboard/amd/crater/chromeos_renoir.fmd b/src/mainboard/amd/crater/chromeos_renoir.fmd new file mode 100644 index 0000000..76a21f6 --- /dev/null +++ b/src/mainboard/amd/crater/chromeos_renoir.fmd @@ -0,0 +1,35 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + WP_RO 8M { + EC_SIG 4K + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + COREBOOT(CBFS) + GBB 448K + } + } + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 256K + RW_LEGACY(CBFS) + EC_BODY@15872K 256K + RW_MRC_CACHE(PRESERVE) 64K + } +} diff --git a/src/mainboard/amd/crater/devicetree_renoir.cb b/src/mainboard/amd/crater/devicetree_renoir.cb new file mode 100644 index 0000000..16d2c7e --- /dev/null +++ b/src/mainboard/amd/crater/devicetree_renoir.cb @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/cezanne + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + # Set FADT Configuration + register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec + + # ACP Configuration + register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_I2S_TDM" + register "common_config.acp_config" = "{ + .acp_pin_cfg = I2S_PINS_I2S_TDM, + .acp_i2s_wake_enable = 0, + .acp_pme_enable = 0, + }" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" + + register "s0ix_enable" = "false" + + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_ON" + register "gpp_clk_config[1]" = "GPP_CLK_ON" + register "gpp_clk_config[2]" = "GPP_CLK_ON" + register "gpp_clk_config[3]" = "GPP_CLK_ON" + register "gpp_clk_config[4]" = "GPP_CLK_ON" + register "gpp_clk_config[5]" = "GPP_CLK_ON" + register "gpp_clk_config[6]" = "GPP_CLK_ON" + + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + device domain 0 on + device ref iommu on end + device ref gpp_gfx_bridge_0 on end #GFX + device ref gpp_gfx_bridge_1 on end + device ref gpp_bridge_0 off end + device ref gpp_bridge_1 off end + device ref gpp_bridge_2 on end + device ref gpp_bridge_3 on end # NVME + device ref gpp_bridge_4 off end + device ref gpp_bridge_5 off end + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # gfx_hda + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port4 on end + end + chip drivers/usb/acpi + device ref usb3_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port6 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + device ref hda on end # Audio Processor HD Audio Controller + end + + device ref gpp_bridge_b on # Internal GPP Bridge 1 to Bus B + device ref sata_0 on end # SATA 0 + device ref sata_1 on end # SATA 1 + device ref xgbe_0 on end # XGBE0 + device ref xgbe_1 on end # XGBE1 + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + device ref uart_1 on end # UART1 + +end diff --git a/src/mainboard/amd/crater/dsdt.asl b/src/mainboard/amd/crater/dsdt.asl new file mode 100644 index 0000000..7b8982a --- /dev/null +++ b/src/mainboard/amd/crater/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include <acpi/dsdt_top.asl> + + #include <soc.asl> +} diff --git a/src/mainboard/amd/crater/early_gpio.c b/src/mainboard/amd/crater/early_gpio.c new file mode 100644 index 0000000..097a61f --- /dev/null +++ b/src/mainboard/amd/crater/early_gpio.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + PAD_GPI(GPIO_3, PULL_UP), + /* TPM CS */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* LPC_PME */ + PAD_NF(GPIO_22, LPC_PME_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST */ + PAD_GPO(GPIO_24, HIGH), + /* DEVSLP1 */ + PAD_NFO(GPIO_6, DEVSLP1, LOW), + + /*I2S SP/BT Audio & Record*/ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_DOWN), + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_DOWN), + + /*MDIO0_SCL*/ + PAD_NF(GPIO_10, MDIO0_SCL, PULL_DOWN), + /*MDIO0_SDA*/ + PAD_NF(GPIO_40, MDIO0_SDA, PULL_DOWN), + /*MDIO1_SCL*/ + PAD_NF(GPIO_9, MDIO1_SCL, PULL_DOWN), + /*MDIO1_SDA*/ + PAD_NF(GPIO_23, MDIO1_SDA, PULL_DOWN), + + + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL*/ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA*/ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c new file mode 100644 index 0000000..b3ef97a --- /dev/null +++ b/src/mainboard/amd/crater/ec.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <gpio.h> +#include "ec.h" + +#define CRATER_EC_CMD 0x666 +#define CRATER_EC_DATA 0x662 + +#define ENABLE_M2_SSD1 1 +#define EC_GPIO_0_ADDR 0xA0 +#define EC_EVAL_PWREN BIT(0) + +#define EC_GPIO_2_ADDR 0xA2 +#define EC2_EVAL_SLOT_PWREN BIT(5) +#define EC2_EVAL_19V_EN BIT(2) +#define EC2_DT_PWREN BIT(6) + +#define EC_GPIO_3_ADDR 0xA3 +#define EC3_WLAN_RST_AUX BIT(5) +#define EC3_WWAN_RST_AUX BIT(4) +#define EC3_SD_RST_AUX BIT(3) +#define EC3_DT_RST BIT(2) +#define EC3_LOM_RST_AUX BIT(1) +#define EC3_EVAL_RST_AUX BIT(0) +#define EC3_TBT_RST BIT(7) + +#define EC_GPIO_4_ADDR 0xA4 +#define EC4_TBT_PWREN BIT(0) + +#define EC_GPIO_7_ADDR 0xA7 +#define EC7_SSD_HDD_SW BIT(5) +#define EC7_ODD_SSD_SW BIT(4) +#define EC7_CAM1_EN BIT(0) + +#define EC_GPIO_8_ADDR 0xA8 +#define EC8_ODD_PWR_EN BIT(0) +#define EC8_HDD_PWR_EN BIT(1) +#define EC8_M2SSD_PWREN BIT(5) +#define EC8_WL_RADIO BIT(6) +#define EC8_BT_RADIO BIT(7) + +#define EC_GPIO_9_ADDR 0xA9 +#define SMBUS1_DEV_MUX_SW BIT(0) // ECRAMxA9[0] +#define SMBUS0_DEV_MUX_SW BIT(1) // ECRAMxA9[1] +#define MUX0_S0 BIT(2) // ECRAMxA9[2] +#define MUX0_S1 BIT(3) // ECRAMxA9[3] +#define MUX1_S0 BIT(4) // ECRAMxA9[4] +#define MUX1_S1 BIT(5) // ECRAMxA9[5] +#define MUX2_S0 BIT(6) // ECRAMxA9[6] +#define MUX2_S1 BIT(7) // ECRAMxA9[7] + + +#define EC_GPIO_A_ADDR 0xAA +#define ECA_MUX2_S0 BIT(7) +#define ECA_MUX2_S1 BIT(6) +#define ECA_MUX1_S0 BIT(5) +#define ECA_MUX1_S1 BIT(4) +#define ECA_MUX0_S0 BIT(3) +#define ECA_MUX0_S1 BIT(2) +#define ECA_SMBUS1_EN BIT(1) +#define ECA_SMBUS0_EN BIT(0) + +#define EC_GPIO_C_ADDR 0xAC +#define ECC_TPNL_BUF_EN BIT(6) +#define ECC_TPAD_BUF_EN BIT(5) +#define ECC_NFC_BUF_EN BIT(4) + +#define EC_GPIO_D_ADDR 0xAD +#define ECD_TPNL_PWR_EN BIT(7) +#define ECD_TPNL_EN BIT(6) +#define ECD_SSD1_PWR_EN BIT(5) +#define ECD_FPR_PWR_EN BIT(3) +#define ECD_FPR_OFF_N BIT(2) +#define ECD_FPR_LOCK_N BIT(1) +#define ECD_TPAD_DISABLE_N BIT(0) + +#define EC_GPIO_E_ADDR 0xAE +#define ECE_LOM_PWR_EN BIT(7) +#define ECE_SSD0_PWR_EN BIT(6) +#define ECE_SD_PWR_EN BIT(5) +#define ECE_WLAN_PWR_EN BIT(4) +#define ECE_WWAN_PWR_EN BIT(3) +#define ECE_CAM_PWR_EN BIT(2) +#define ECE_FPR_N_GBE_SEL BIT(1) +#define ECE_BT_N_TPNL_SEL BIT(0) + +#define EC_GPIO_F_ADDR 0xAF +#define ECF_CAM_FW_WP_N BIT(7) +#define ECF_I2C_MUX_OE_N BIT(4) +#define ECF_WLAN0_N_WWAN1_SW BIT(1) +#define ECF_WWAN0_N_WLAN1_SW BIT(0) + +#define EC_GPIO_G_ADDR 0xB0 +#define ECG_IR_LED_PWR_EN BIT(7) +#define ECG_U0_WLAN_HDR_SEL BIT(6) +#define ECG_DT_SSD1_MUX_OFF BIT(5) +#define ECG_WLAN_WWAN_MUX_OFF BIT(4) + +#define ECRAM_BOARDID_OFFSET 0x93 +#define CRATER_REVB 0x42 + +static void configure_ec_gpio(void) +{ + uint8_t tmp; + + tmp = ec_read(EC_GPIO_2_ADDR); + printk(BIOS_SPEW, "A2: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp); + if (CONFIG(ENABLE_EVAL_CARD)) { + tmp |= EC2_EVAL_SLOT_PWREN; + if (CONFIG(ENABLE_EVAL_19V)) { + tmp |= EC2_EVAL_19V_EN; + } else { + tmp &= ~EC2_EVAL_19V_EN; + } + } else { + tmp &= ~EC2_EVAL_SLOT_PWREN; + tmp &= ~EC2_EVAL_19V_EN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp); + ec_write(EC_GPIO_2_ADDR, tmp); + + tmp = ec_read(EC_GPIO_7_ADDR); + printk(BIOS_SPEW, "A7: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp); + if (ENABLE_M2_SSD1) { + tmp |= (EC7_ODD_SSD_SW|EC7_SSD_HDD_SW); + } else { + tmp &= ~(EC7_ODD_SSD_SW|EC7_SSD_HDD_SW); + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp); + ec_write(EC_GPIO_7_ADDR, tmp); + + tmp = ec_read(EC_GPIO_8_ADDR); + printk(BIOS_SPEW, "A8: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); + if (ENABLE_M2_SSD1) { + tmp |= EC8_M2SSD_PWREN; + } else { + tmp &= ~EC8_M2SSD_PWREN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); + ec_write(EC_GPIO_8_ADDR, tmp); +} + +static const struct soc_amd_gpio RevA_gpio_set_stage_ram[] = { + /* PCIE x8 SLOT*/ + PAD_GPO(GPIO_4, HIGH), +}; + +static const struct soc_amd_gpio RevB_gpio_set_stage_ram[] = { + PAD_GPI(GPIO_4, PULL_UP), + PAD_GPO(GPIO_12, LOW), +}; + +void crater_boardrevision(void) +{ + uint8_t BoardRev; + BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3); + + if (BoardRev == CRATER_REVB) + gpio_configure_pads(RevB_gpio_set_stage_ram, ARRAY_SIZE(RevB_gpio_set_stage_ram)); + else + gpio_configure_pads(RevA_gpio_set_stage_ram, ARRAY_SIZE(RevA_gpio_set_stage_ram)); +} + +void crater_ec_init(void) +{ + ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); + crater_boardrevision(); + configure_ec_gpio(); +} diff --git a/src/mainboard/amd/crater/ec.h b/src/mainboard/amd/crater/ec.h new file mode 100644 index 0000000..9dd5cbc --- /dev/null +++ b/src/mainboard/amd/crater/ec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CRATER_EC_H +#define CRATER_EC_H + +void crater_ec_init(void); +void crater_boardrevision(void); + +#endif /* CRATER_EC_H */ diff --git a/src/mainboard/amd/crater/gpio.c b/src/mainboard/amd/crater/gpio.c new file mode 100644 index 0000000..27b045c --- /dev/null +++ b/src/mainboard/amd/crater/gpio.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + PAD_GPI(GPIO_3, PULL_UP), + /* TPM CS */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* LPC_PME */ + PAD_NF(GPIO_22, LPC_PME_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST */ + PAD_GPO(GPIO_24, HIGH), + /* DEVSLP1 */ + PAD_NFO(GPIO_6, DEVSLP1, LOW), + + /*I2S SP/BT Audio & Record*/ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_DOWN), + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_DOWN), + + /*MDIO0_SCL*/ + PAD_NF(GPIO_10, MDIO0_SCL, PULL_DOWN), + /*MDIO0_SDA*/ + PAD_NF(GPIO_40, MDIO0_SDA, PULL_DOWN), + /*MDIO1_SCL*/ + PAD_NF(GPIO_9, MDIO1_SCL, PULL_DOWN), + /*MDIO1_SDA*/ + PAD_NF(GPIO_23, MDIO1_SDA, PULL_DOWN), + + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* I2C2_SCL*/ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL*/ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA*/ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +}; + +void mainboard_program_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/crater/gpio.h b/src/mainboard/amd/crater/gpio.h new file mode 100644 index 0000000..04c98c5 --- /dev/null +++ b/src/mainboard/amd/crater/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/crater/mainboard.c b/src/mainboard/amd/crater/mainboard.c new file mode 100644 index 0000000..eb13e07 --- /dev/null +++ b/src/mainboard/amd/crater/mainboard.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpi.h> +#include <amdblocks/amd_pci_util.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <types.h> +#include "gpio.h" + +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_program_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c new file mode 100644 index 0000000..bcddf1e --- /dev/null +++ b/src/mainboard/amd/crater/port_descriptors_renoir.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <soc/cpu.h> +#include <types.h> +#include <amdblocks/cpu.h> +#include <soc/pci_devs.h> +#include <console/console.h> +#include <ec/acpi/ec.h> +#include <stdint.h> + +#define ECRAM_MACID_OFFSET 0x54 +#define MACID_LEN 12 + +#define ECRAM_BOARDID_OFFSET 0x93 + +#define CRATER_EC_CMD 0x666 +#define CRATER_EC_DATA 0x662 + +#define CRATER_REVB 0x42 + +static const fsp_dxio_descriptor crater_dxio_descriptors[] = { + { /* MXM */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = false, + .clk_req = CLK_REQ0, + .gpio_group_id = GPIO_4, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 4, + .link_aspm = ASPM_DISABLED, + .link_aspm_L1_1 = false, + .link_aspm_L1_2 = false, + .turn_off_unused_lanes = false, + .clk_req = CLK_REQ3, + .gpio_group_id = GPIO_27, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, +}; + +static fsp_ddi_descriptor crater_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + uint8_t BoardRev; + + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + crater_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; + + ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); + BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3); + + if (CONFIG(ENABLE_EDP)) { + crater_ddi_descriptors[1].connector_type = DDI_EDP; + } else { + if (BoardRev == CRATER_REVB) + crater_ddi_descriptors[1].connector_type = DDI_DP; + else + crater_ddi_descriptors[1].connector_type = DDI_HDMI; + } + + *dxio_descs = crater_dxio_descriptors; + *dxio_num = ARRAY_SIZE(crater_dxio_descriptors); + *ddi_descs = crater_ddi_descriptors; + *ddi_num = ARRAY_SIZE(crater_ddi_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 11 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral

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[S] Change in coreboot[main]: soc/amd/cezanne: add option to disable I2S master clock output of FCH
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85865?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/cezanne: add option to disable I2S master clock output of FCH ...................................................................... soc/amd/cezanne: add option to disable I2S master clock output of FCH Add a devicetree option to disable the 48MHz clock output of the FCH when an I2S audio codec uses a separate oscillator for its 48 MHz master clock instead of the FCH clock output. This code was ported from the Picasso code base. Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85865 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 2 files changed, 12 insertions(+), 2 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index a8b7f22..738282f 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -108,6 +108,9 @@ uint8_t tx_eq_post; uint8_t tx_vboost_lvl; } edp_tuningset; + + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ + bool acp_i2s_use_external_48mhz_osc; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index b9f529d..0690eb7 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -83,8 +83,15 @@ static void fch_clk_output_48Mhz(void) { uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); - /* Enable BP_X48M0 Clock Output */ - ctrl |= BP_X48M0_OUTPUT_EN; + const struct soc_amd_cezanne_config *cfg = config_of_soc(); + + /* If using external clock source for I2S, disable the internal clock output */ + if (cfg->acp_i2s_use_external_48mhz_osc && + cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM) + ctrl &= ~BP_X48M0_OUTPUT_EN; + else + ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ ctrl |= BP_X48M0_S0I3_DIS; misc_write32(MISC_CLK_CNTL0, ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/85865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Gerrit-Change-Number: 85865 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Kochlowski <nickkochlowski(a)gmail.com>

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[XS] Change in coreboot[main]: src/soc/amd/glinda: Update PSP MBOX offset in Kconfig
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85627?usp=email ) Change subject: src/soc/amd/glinda: Update PSP MBOX offset in Kconfig ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85627/comment/9b909f78_98e14413?us… : PS3, Line 10: since Ana tested this on birman+ with a glinda soc, it would be good to add the test result to this commit message. see the comment on the previous patch in the patch train -- To view, visit https://review.coreboot.org/c/coreboot/+/85627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I328959513228fe0f9e78070eb6b302ef89857b42 Gerrit-Change-Number: 85627 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 12:48:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/common/psp_gen2: Add config for PSP MBOX offset
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85626?usp=email ) Change subject: soc/amd/common/psp_gen2: Add config for PSP MBOX offset ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS1: > Tested with Birman Plus and it solved the issue for psp timeout […] would be good to have this info added to the commit message of the following patch that changes this for glinda -- To view, visit https://review.coreboot.org/c/coreboot/+/85626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211 Gerrit-Change-Number: 85626 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 12:47:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Ana Carolina Cabral

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control
by Subrata Banik (Code Review) 10 Jan '25

10 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85934?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP log level control ...................................................................... soc/intel/pantherlake: Refactor FSP log level control Refactor the FSP log level control by introducing a helper function `fsp_set_debug_level()` to set the serial and MRC debug levels. This change improves code readability and maintainability by separating the log level setting logic from the main control flow. It also adds a check to ensure the configured log levels are valid. Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 22 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85934/1 diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 57954e0..d2724fe 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -296,6 +296,15 @@ fill_fspm_params[i](m_cfg, config); } +static void fsp_set_debug_level(FSP_M_CONFIG *m_cfg, + enum fsp_log_level fsp_pcd_log_level, enum fsp_log_level fsp_mrc_log_level) +{ + /* Set Serial debug message level */ + m_cfg->PcdSerialDebugLevel = fsp_pcd_log_level; + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = fsp_mrc_log_level; +} + static void fsp_control_log_level(FSPM_UPD *mupd, bool is_enabled) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -303,17 +312,21 @@ if (is_enabled) { enum fsp_log_level log_level = fsp_map_console_log_level(); - arch_upd->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); - /* Set Serial debug message level */ - m_cfg->PcdSerialDebugLevel = log_level; - /* Set MRC debug level */ - m_cfg->SerialDebugMrcLevel = log_level; + fsp_set_debug_level(m_cfg, log_level, log_level); } else { - /* Disable Serial debug message */ - m_cfg->PcdSerialDebugLevel = 0; - /* Disable MRC debug message */ - m_cfg->SerialDebugMrcLevel = 0; + /* Disable Serial/MRC debug message */ + fsp_set_debug_level(m_cfg, 0, 0); } + + if ((m_cfg->PcdSerialDebugLevel > FSP_LOG_LEVEL_VERBOSE) || + (m_cfg->SerialDebugMrcLevel > FSP_LOG_LEVEL_VERBOSE)) { + printk(BIOS_ERR, "Invalid FSP log level\n"); + return; + } + + /* Set Event Handler if log-level is non-zero */ + if (m_cfg->PcdSerialDebugLevel || m_cfg->SerialDebugMrcLevel) + arch_upd->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); } static void fill_fsp_event_handler(FSPM_UPD *mupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/85934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Gerrit-Change-Number: 85934 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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