coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat
by Pranava Y N (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Subrata Banik. Pranava Y N has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85999?usp=email ) Change subject: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Gerrit-Change-Number: 85999 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 08:15:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat
by Jayvik Desai (Code Review) 15 Jan '25

15 Jan '25

Jayvik Desai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85999?usp=email ) Change subject: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat ...................................................................... MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85999/1 diff --git a/MAINTAINERS b/MAINTAINERS index 45bcac0..6f2f5d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -354,6 +354,7 @@ GOOGLE FATCAT MAINBOARDS M: Subrata Banik <subratabanik(a)google.com> M: Pranava Y N <pranavayn(a)google.com> +M: Jayvik Desai <jayvik(a)google.com> F: src/mainboard/google/fatcat/ GOOGLE HATCH MAINBOARDS @@ -927,6 +928,7 @@ M: Subrata Banik <subratabanik(a)google.com> M: Kapil Porwal <kapilporwal(a)google.com> M: Pranava Y N <pranavayn(a)google.com> +M: Jayvik Desai <jayvik(a)google.com> S: Maintained F: src/soc/intel/pantherlake/ -- To view, visit https://review.coreboot.org/c/coreboot/+/85999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Gerrit-Change-Number: 85999 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add display driver
by Nancy Lin (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Nancy Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add display driver ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/e6aec04f_515ded54?us… : PS2, Line 308: > After check HW spec, some engines's w/h is 16 bits, some are 13 bits. […] Sorry, I think I need to check 13bit for the whole path support width <= 0x1FFF && height <= 0x1FFF -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 07:52:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/google/rex/var/kanix: Update CPU power limit
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Kenneth Chan, Tarun. Subrata Banik has posted comments on this change by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/85998?usp=email ) Change subject: mb/google/rex/var/kanix: Update CPU power limit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096 Gerrit-Change-Number: 85998 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 07:27:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/lenovo/x131e: Remove old USB configurations
by Patrick Rudolph (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85944?usp=email ) Change subject: mb/lenovo/x131e: Remove old USB configurations ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 07:14:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/lenovo/t530: Remove old USB configurations
by Patrick Rudolph (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85943?usp=email ) Change subject: mb/lenovo/t530: Remove old USB configurations ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85943?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2 Gerrit-Change-Number: 85943 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 07:14:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rex/var/kanix: Update CPU power limit
by Kenneth Chan (Code Review) 14 Jan '25

14 Jan '25

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85998?usp=email ) Change subject: mb/google/rex/var/kanix: Update CPU power limit ...................................................................... mb/google/rex/var/kanix: Update CPU power limit Update PL1/PL2/PL4 settings for kanix thermal design PL1_min = 12W PL1_max = 18W PL2 = 40W PL4 = 84W BUG=b:389726952 BRANCH=firmware-rex-15709.B TEST=build success and thermal team's confirm Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/kanix/Makefile.mk M src/mainboard/google/rex/variants/kanix/overridetree.cb A src/mainboard/google/rex/variants/kanix/ramstage.c 3 files changed, 88 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85998/1 diff --git a/src/mainboard/google/rex/variants/kanix/Makefile.mk b/src/mainboard/google/rex/variants/kanix/Makefile.mk index 2638540..03a1836 100644 --- a/src/mainboard/google/rex/variants/kanix/Makefile.mk +++ b/src/mainboard/google/rex/variants/kanix/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 0d76351..a8ca721 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -40,6 +40,12 @@ chip soc/intel/meteorlake + register "power_limits_config[MTL_P_282_242_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 40, + .tdp_pl4 = 84, + }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 @@ -218,15 +224,15 @@ ## Power Limits Control register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 15000, + .min_power = 12000, + .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 57000, - .max_power = 57000, + .min_power = 40000, + .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, diff --git a/src/mainboard/google/rex/variants/kanix/ramstage.c b/src/mainboard/google/rex/variants/kanix/ramstage.c new file mode 100644 index 0000000..87efbca --- /dev/null +++ b/src/mainboard/google/rex/variants/kanix/ramstage.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ + +const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, +}; + +const struct cpu_tdp_power_limits variant_power_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, +}; + +void variant_devtree_update(void) +{ + const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits; + size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits); + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the performance efficient configuration, boot with + * the power optimized configuration. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_chromeec_is_battery_present_and_above_critical_threshold()) { + limits = variant_power_efficient_limits; + limits_size = ARRAY_SIZE(variant_power_efficient_limits); + } + } + + variant_update_cpu_power_limits(limits, limits_size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096 Gerrit-Change-Number: 85998 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Update cache info
by Naresh Solanki (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Angel Pons, Jérémy Compostella. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Update cache info ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85640/comment/fbd41f9f_e21820d3?us… : PS3, Line 8: > Could you please describe why this had to be updated? I'm not familiar with the cache hierarchy on t […] Previously Cache size of only BSP was reported. In case of Glinda, L3 caches is 16 + 8 shared between Classic & Dense cores. Thus requiring alternate approach to identify cache size. File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/ada77794_48b4fa66?us… : PS3, Line 66: memcpy(info, &info_list[0], sizeof(*info)); > Out of curiosity, is this copy necessary? This part may need some optimisation. The caller expect data for as part of struct info. Here we take this as sample from info_list[0] & manupalate size based on id so that as end result, smbios reports right amount of cache size. -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 07:07:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Naresh Solanki (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Felix Held, Jérémy Compostella. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/85639/comment/a9e965b5_e150d207?us… : PS1, Line 280: uint8_t > this should probably be a larger int type than uint8_t, since we might have more than 256 cores in t […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 15 Jan 2025 07:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: arch/x86/cpu: Mark fill_cpu_cache_info as weak
by Naresh Solanki (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Mark fill_cpu_cache_info as weak ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/85638/comment/8059258d_e50fda2b?us… : PS1, Line 224: struct cpuid_result cache_info_res = cpuid_ext(leaf, level); : : info->type = CPUID_CACHE_TYPE(cache_info_res); : info->level = CPUID_CACHE_LEVEL(cache_info_res); : info->num_ways = CPUID_CACHE_WAYS_OF_ASSOC(cache_info_res) + 1; : info->num_sets = CPUID_CACHE_NO_OF_SETS(cache_info_res) + 1; : info->line_size = CPUID_CACHE_COHER_LINE(cache_info_res) + 1; : info->physical_partitions = CPUID_CACHE_PHYS_LINE(cache_info_res) + 1; : info->num_cores_shared = CPUID_CACHE_SHARING_CACHE(cache_info_res) + 1; : info->fully_associative = CPUID_CACHE_FULL_ASSOC(cache_info_res); : info->size = get_cache_size(info); : > Looking at follow-ups, would it make sense to extract this part into a helper function? Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:59:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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coreboot-gerrit January 2025