coreboot-gerrit January 2025

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Nicholas Chin. Subrata Banik has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Nicholas, I'm going to address the review comments in this CL since we need this option to read the API for CrOS work. I hope you don't mind me touching your code. -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 04:28:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek: Skip duplicate pmif_arb->is_pmif_init_done() call
by Yidi Lin (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85967?usp=email ) Change subject: soc/mediatek: Skip duplicate pmif_arb->is_pmif_init_done() call ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/common/mt6315.c: https://review.coreboot.org/c/coreboot/+/85967/comment/1b922476_184e26ad?us… : PS2, Line 92: ! Fix the wrong condition. -- To view, visit https://review.coreboot.org/c/coreboot/+/85967?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1d11f8b238855edb393d77151159792e7716d22 Gerrit-Change-Number: 85967 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 04:25:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek: Skip duplicate pmif_arb->is_pmif_init_done() call
by Yidi Lin (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85967?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/mediatek: Skip duplicate pmif_arb->is_pmif_init_done() call ...................................................................... soc/mediatek: Skip duplicate pmif_arb->is_pmif_init_done() call Return to the caller immediately if pmif_arb has been initiailized. In this way, we can skip unnecessary check and reduce the access to the PMIF register. TEST=emerge-geralt coreboot && emerge-rauru coreboot Change-Id: Id1d11f8b238855edb393d77151159792e7716d22 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/mt6315.c M src/soc/mediatek/common/mt6316.c M src/soc/mediatek/common/mt6359p.c M src/soc/mediatek/common/mt6363.c M src/soc/mediatek/common/mt6373.c M src/soc/mediatek/common/mt6685.c 6 files changed, 31 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85967/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85967?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1d11f8b238855edb393d77151159792e7716d22 Gerrit-Change-Number: 85967 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS
by Bora Guvendik (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Pranava Y N, Subrata Banik. Bora Guvendik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85992?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9883036b5e964cb55bd34c36398a501f69a8ecaa Gerrit-Change-Number: 85992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 03:52:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/nissa/var/dirks: Add initial override devicetree
by Ivy Jian (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85991?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/dirks: Add initial override devicetree ...................................................................... mb/google/nissa/var/dirks: Add initial override devicetree Add initial override devicetree for riven based on the latest schematic (0W4_TWL_A_MB_0113.pdf). - Add eMMC DLL tuning value (copy from riven) - Configure I2C buses - Configure USB ports - Configure audio codec - Configure WIFI6(CNVi) and WIFI7(PCIe) USB Ports for dirks: (FRONT) USBA 10G x 3 (REAR) USBA 10G x 2 + USBC 10G x 1 Note : repurpose the TCSS port 1 to USB3.2 Gen2x1 Type-A (Document Number: 742076) BUG=b:388117663 TEST=none. Change-Id: Ib227995cde8d871ff58c89ccb09221226640a7e6 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dirks/Makefile.mk M src/mainboard/google/brya/variants/dirks/overridetree.cb A src/mainboard/google/brya/variants/dirks/ramstage.c 3 files changed, 358 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/85991/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib227995cde8d871ff58c89ccb09221226640a7e6 Gerrit-Change-Number: 85991 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85992?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS ...................................................................... mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS There is an issue where the codec enable signal is not working correctly when FPS (Fingerprint Sensor) is enabled. This commit applies a temporary workaround by using a dedicated GPIO pin for codec enable. This allows the codec to function properly even when FPS is enabled, preventing audio issues. A proper fix in hardware schematics will be implemented in a future update. BUG=b:390031369 TEST=Verified audio playback works with FPS being enabled. Change-Id: I9883036b5e964cb55bd34c36398a501f69a8ecaa Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85992/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 0ba6048..3e6a192 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -443,7 +443,12 @@ PAD_NC(GPP_C15, NONE), /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ PAD_CFG_GPO(GPP_D01, 1, DEEP), - PAD_NC(GPP_E19, NONE), + /* FIXME: b/390031369 + * use dedicated GPIO PIN for codec enable + * when FPS is enabled. + */ + /* GPP_E19: CODEC_EN */ + PAD_CFG_GPO(GPP_E19, 1, PLTRST), PAD_NC(GPP_E20, NONE), PAD_NC(GPP_F14, NONE), PAD_NC(GPP_F15, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/85992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9883036b5e964cb55bd34c36398a501f69a8ecaa Gerrit-Change-Number: 85992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85958?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support ...................................................................... mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support Refactor GPIO programming to support UFS storage on the fatcat platform. - Add pad configurations for UFS in `fw_config.c`. - Update `fw_config_configure_pre_mem_gpio()` and `fw_config_gpio_padbased_override()` to include UFS support. - Remove redundant UFS pad configuration from `gpio.c`. TEST=Able to build and boot from UFS device on google/fatcat. Change-Id: I09331d75501977d89592d1a70d5b0dca271f8747 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85958 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c 2 files changed, 10 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index ac2155f..0ba6048 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -210,6 +210,11 @@ PAD_CFG_GPO(GPP_B09, 1, PLTRST), }; +static const struct pad_config ufs_enable_pads[] = { + /* GPP_D21: GPP_D21_UFS_REFCLK */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +}; + /* Gen5 NVME: at the bottom M.2 slot */ static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = { /* GPP_B16: GEN5_SSD_PWREN */ @@ -484,12 +489,9 @@ GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); - /* TODO: else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) - */ } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); - /* TODO for UFS */ } if (!fw_config_probe(FW_CONFIG(SD, SD_NONE))) @@ -524,12 +526,12 @@ GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); - /* TODO: else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) - */ + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); - /* TODO for UFS */ + GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); } if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index d6fea09..cf1e040 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -175,8 +175,8 @@ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D20: CSE_EARLY_SW */ PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL), - /* GPP_D21: GPP_D21_UFS_REFCLK */ - PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* GPP_D21: NC */ + PAD_NC(GPP_D21, NONE), /* GPP_D22: BPKI3C_SDA */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* GPP_D23: BPKI3C_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09331d75501977d89592d1a70d5b0dca271f8747 Gerrit-Change-Number: 85958 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Drop UFC/WFC GPIO programming
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85955?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat/var/fatcat: Drop UFC/WFC GPIO programming ...................................................................... mb/google/fatcat/var/fatcat: Drop UFC/WFC GPIO programming Skip UFC/WFC GPIO programming for power-on and clock configuration. Clock configuration is now handled by native-function in ramstage, and there is no need to power-on the camera module early in the boot phase. Doing so resulted in the privacy LED being turned on during the entire boot process, which is unnecessary. BUG=b:381044394 TEST=No privacy LED blinking seen while booting google/fatcat. Change-Id: Iae984a2ab6f797af450166c90f4a2c6d3e0e1caa Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85955 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c 2 files changed, 0 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 87f9097..ac2155f 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -223,46 +223,6 @@ PAD_CFG_GPO(GPP_E03, 1, PLTRST), }; -/* camera1: WFC */ -static const struct pad_config pre_mem_wfc_camera_pwr_pads[] = { - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 0, PLTRST), -}; - -static const struct pad_config wfc_camera_enable_pads[] = { - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 1, PLTRST), - /* GPP_D04: IMGCLKOUT_0 */ - PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), -}; - -static const struct pad_config wfc_camera_disable_pads[] = { - /* GPP_C05: CRD1_PWREN */ - PAD_NC(GPP_C05, NONE), - /* GPP_D04: IMGCLKOUT_0 */ - PAD_NC(GPP_D04, NONE), -}; - -/* camera2: UFC */ -static const struct pad_config pre_mem_ufc_camera_pwr_pads[] = { - /* GPP_C08: CRD2_PWREN */ - PAD_CFG_GPO(GPP_C08, 0, PLTRST), -}; - -static const struct pad_config ufc_camera_enable_pads[] = { - /* GPP_C08: CRD2_PWREN */ - PAD_CFG_GPO(GPP_C08, 1, PLTRST), - /* GPP_D00: IMGCLKOUT_1 */ - PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), -}; - -static const struct pad_config ufc_camera_disable_pads[] = { - /* GPP_C08: CRD2_PWREN */ - PAD_NC(GPP_C08, NONE), - /* GPP_D00: IMGCLKOUT_1 */ - PAD_NC(GPP_D00, NONE), -}; - static const struct pad_config peg_x4slot_wake_disable_pads[] = { /* GPP_D24: PEG_SLOT_WAKE_N */ PAD_NC(GPP_D24, NONE), @@ -520,12 +480,6 @@ if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); - if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) - GPIO_CONFIGURE_PADS(pre_mem_wfc_camera_pwr_pads); - - if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) - GPIO_CONFIGURE_PADS(pre_mem_ufc_camera_pwr_pads); - if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { @@ -578,16 +532,6 @@ /* TODO for UFS */ } - if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) - GPIO_PADBASED_OVERRIDE(padbased_table, wfc_camera_enable_pads); - else - GPIO_PADBASED_OVERRIDE(padbased_table, wfc_camera_disable_pads); - - if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) - GPIO_PADBASED_OVERRIDE(padbased_table, ufc_camera_enable_pads); - else - GPIO_PADBASED_OVERRIDE(padbased_table, ufc_camera_disable_pads); - if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads); else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 881c5c7..d6fea09 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -108,14 +108,10 @@ PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* GPP_C04: TCP_LAN_SML0_SDA_R */ PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 1, PLTRST), /* GPP_C06: SML1_CLK */ PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), /* GPP_C07: SML1_DATA */ PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), - /* GPP_C08: CRD2_PWREN */ - PAD_CFG_GPO(GPP_C08, 1, PLTRST), /* GPP_C09: CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */ PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), /* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae984a2ab6f797af450166c90f4a2c6d3e0e1caa Gerrit-Change-Number: 85955 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Configure _DSC for camera devices
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85954?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Configure _DSC for camera devices ...................................................................... mb/google/fatcat/var/fatcat: Configure _DSC for camera devices Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD for camera devices to prevent them from being probed during kernel boot. This prevents the privacy LED from blinking unnecessarily. Also includes minor code comment changes for clarity: - Replace "560000000" with "560 * MHz" for readability. - Explain `clknum` value `0` as `IMGCLKOUT_0` and `1` as `IMGCLKOUT_1`. - Introduce FW_CONFIG (UFC/WFC) for probing IPU0. BUG=b:381044394 TEST=No privacy LED blinking seen while rebooting google/fatcat. Change-Id: I4712b751015d86d40dfd4d7da8cba956c435eef5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85954 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 1 file changed, 71 insertions(+), 10 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 19fbff8..5414e15 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -302,12 +302,15 @@ register "acpi_name" = ""IPU0"" register "device_type" = "INTEL_ACPI_CAMERA_CIO2" register "cio2_num_ports" = "2" - register "cio2_lanes_used" = "{4,2}" + register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0"" register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1"" register "cio2_prt[0]" = "0" register "cio2_prt[1]" = "2" - device generic 0 on end + device generic 0 on + probe UFC UFC_MIPI + probe WFC WFC_MIPI + end end end @@ -604,12 +607,13 @@ register "ssdb.lanes_used" = "4" register "num_freq_entries" = "1" - register "link_freq[0]" = "560000000" + register "link_freq[0]" = "560 * MHz" # 560 MHz register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "true" #Controls - register "clk_panel.clks[0].clknum" = "0" + register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset @@ -637,9 +641,23 @@ register "chip_name" = ""DW AF VCM"" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on probe WFC WFC_MIPI end @@ -650,7 +668,6 @@ register "chip_name" = ""BRCA016GWZ"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" register "nvm_compat" = ""atmel,24c16"" register "nvm_size" = "0x800" @@ -658,6 +675,21 @@ register "nvm_readonly" = "0x01" register "nvm_width" = "0x08" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 50 on probe WFC WFC_MIPI end @@ -676,12 +708,13 @@ register "ssdb.lanes_used" = "2" register "num_freq_entries" = "1" - register "link_freq[0]" = "560000000" + register "link_freq[0]" = "560 * MHz" # 560 MHz register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "true" #Controls - register "clk_panel.clks[0].clknum" = "1" + register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset @@ -709,9 +742,23 @@ register "chip_name" = ""DW AF VCM"" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on probe UFC UFC_MIPI end @@ -722,7 +769,6 @@ register "chip_name" = ""BRCA016GWZ"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" register "nvm_compat" = ""atmel,24c16"" register "nvm_size" = "0x800" @@ -730,6 +776,21 @@ register "nvm_readonly" = "0x01" register "nvm_width" = "0x08" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 50 on probe UFC UFC_MIPI end -- To view, visit https://review.coreboot.org/c/coreboot/+/85954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4712b751015d86d40dfd4d7da8cba956c435eef5 Gerrit-Change-Number: 85954 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD
by Subrata Banik (Code Review) 14 Jan '25

14 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85953?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD ...................................................................... mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. TEST=Able to verify display using all the display end-point device. Change-Id: I32f74411aa80279d63c3b12087ffc47b33fcc039 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85953 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 37ba330..bb1f259 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_FATCAT_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 95a142f..19fbff8 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -146,6 +146,28 @@ device domain 0 on device ref igpu on probe DISPLAY DISPLAY_PRESENT + chip drivers/gfx/generic + register "device_count" = "5" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device generic 0 on end + end end device ref dtt on -- To view, visit https://review.coreboot.org/c/coreboot/+/85953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f74411aa80279d63c3b12087ffc47b33fcc039 Gerrit-Change-Number: 85953 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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