coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: soc/amd/glinda/cpu: smbios: update external clock
by Naresh Solanki (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Felix Held. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85636?usp=email ) Change subject: soc/amd/glinda/cpu: smbios: update external clock ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > does this only apply to Glinda or to all or at least more of the newer AMD SoCs? I dont have the exact information about other SoC as of now. -- To view, visit https://review.coreboot.org/c/coreboot/+/85636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f73695019612d58b0c78c6985370d23c78b729 Gerrit-Change-Number: 85636 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:58:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add display driver
by Nancy Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Nancy Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add display driver ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/e867056b_4dee475b?us… : PS2, Line 308: > OK, I will fix it After check HW spec, some engines's w/h is 16 bits, some are 13 bits. So Can I check only width <= 0xFFFF && height <= 0xFFFF -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:56:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85905?usp=email to look at the new patch set (#6). Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in cbfs with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -i option/value -n option_name`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 51 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85905/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: mb/lenovo/x131e: Remove old USB configurations
by Patrick Rudolph (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85944?usp=email ) Change subject: mb/lenovo/x131e: Remove old USB configurations ...................................................................... Patch Set 2: (1 comment) File src/mainboard/lenovo/x131e/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85944/comment/17da48ea_f4f6789c?us… : PS2, Line 45: 0x00000c03 according to schematics P0 and P1 are the only USB3.0 ports and both connected to OC0#. `struct southbridge_usb_port mainboard_usb_ports ` seem to be correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:21:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lenovo/t400: Add ThinkPad T400s as a variant
by Bill XIE (Code Review) 15 Jan '25

15 Jan '25

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85997?usp=email ) Change subject: mb/lenovo/t400: Add ThinkPad T400s as a variant ...................................................................... mb/lenovo/t400: Add ThinkPad T400s as a variant It is more similar to X301 than to T400, but it shares BDC detection PIN with T400, while using different HDA chip and has no SuperIO. The laptop works well under coreboot with SeaBIOS 1.16.3 payload, running PureOS with Linux kernel 5.10.0. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ic96696921d5a5542a42226c24f7fae253acc4698 --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t400s.md A Documentation/mainboard/lenovo/t400s_flash.jpg M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/Kconfig.name M src/mainboard/lenovo/t400/Makefile.mk M src/mainboard/lenovo/t400/devicetree.cb C src/mainboard/lenovo/t400/variants/r500/hda_verb.c M src/mainboard/lenovo/t400/variants/r500/overridetree.cb R src/mainboard/lenovo/t400/variants/t400/hda_verb.c M src/mainboard/lenovo/t400/variants/t400/overridetree.cb A src/mainboard/lenovo/t400/variants/t400s/board_info.txt A src/mainboard/lenovo/t400/variants/t400s/data.vbt A src/mainboard/lenovo/t400/variants/t400s/gpio.c A src/mainboard/lenovo/t400/variants/t400s/hda_verb.c A src/mainboard/lenovo/t400/variants/t400s/overridetree.cb 16 files changed, 299 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85997/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1bbacaf..93ab450 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -189,6 +189,7 @@ X200 / T400 / T500 / X301 common <lenovo/montevina_series.md> X301 <lenovo/x301.md> +T400s <lenovo/t400s.md> ``` ### Arrandale series diff --git a/Documentation/mainboard/lenovo/t400s.md b/Documentation/mainboard/lenovo/t400s.md new file mode 100644 index 0000000..7eef4c1 --- /dev/null +++ b/Documentation/mainboard/lenovo/t400s.md @@ -0,0 +1,53 @@ +# Lenovo T400s + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + +![T400s with WSON8 chip replaced with SOIC8 chip](t400s_flash.jpg) + +* Battery pack +* RAM lid +* Left DIMM on Slot-1 +* PCI Express Mini Card on wireless WAN socket + +Its [Hardware Maintenance Manual](https://download.lenovo.com/pccbbs/mobiles_pdf/45m2271_01.pdf) can be used as a guidance of disassembly. + +The WSON-8 flash chip (surrounded with red circle in the photo above, +already replaced with a SOIC-8 one) sits between the left DIMM and +the wireless WAN card under two pieces of insulating tape. If solders +between the chip and soldering pads fortunately overflows beside the +chip as tiny tin balls attached to soldering pads, it will be +possible to use a pomona 5250 clip to hold the chip, with its metal +tips just attached to tin balls, thus connecting the chip to the +programmer. Otherwise, it may be recommended to replace it with a +SOIC-8 one (you might need to add the chip to the IFD VSCC list), as +what is done in the photo. + +The vendor IFD VSCC list contains: +- MACRONIX_MX25L6405 (0xc2, 0x2017) +- WINBOND_NEX_W25X64 (0xef, 0x3017) +- ATMEL_AT25DF641 (0x1f, 0x4800) + +The general [flashing tutorial] has more details. + +Tested: +- Core 2 Duo P9600 CPU +- Slotted DIMM 4GiB*2 from Hynix +- Camera +- PCI-e and ExpressCard slots +- SATA, ESATAp and USB2 +- libgfxinit-based graphics init +- NVRAM options for North and South bridges +- Sound +- ThinkPad EC +- Linux 5.10.0-23 within PureOS, loaded from SeaBIOS. + +Known issues: +- Drives hot-swapped to ESATAp port are not detected automatically, + and not considered removable after detected with a manual scan +- S3 resume is unstable + + +[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md + diff --git a/Documentation/mainboard/lenovo/t400s_flash.jpg b/Documentation/mainboard/lenovo/t400s_flash.jpg new file mode 100644 index 0000000..c82e6ac --- /dev/null +++ b/Documentation/mainboard/lenovo/t400s_flash.jpg Binary files differ diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 5afcde8..8a9cff8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 \ - || BOARD_LENOVO_W500 || BOARD_LENOVO_R500 + || BOARD_LENOVO_W500 || BOARD_LENOVO_R500 || BOARD_LENOVO_T400S config BOARD_SPECIFIC_OPTIONS def_bool y @@ -48,9 +48,11 @@ default "t400" if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 \ || BOARD_LENOVO_R400 || BOARD_LENOVO_W500 default "r500" if BOARD_LENOVO_R500 + default "t400s" if BOARD_LENOVO_T400S config MAINBOARD_PART_NUMBER default "ThinkPad T400" if BOARD_LENOVO_T400 + default "ThinkPad T400s" if BOARD_LENOVO_T400S default "ThinkPad T500" if BOARD_LENOVO_T500 default "ThinkPad R400" if BOARD_LENOVO_R400 default "ThinkPad R500" if BOARD_LENOVO_R500 diff --git a/src/mainboard/lenovo/t400/Kconfig.name b/src/mainboard/lenovo/t400/Kconfig.name index 13c5d63..37bd67a 100644 --- a/src/mainboard/lenovo/t400/Kconfig.name +++ b/src/mainboard/lenovo/t400/Kconfig.name @@ -3,6 +3,9 @@ config BOARD_LENOVO_T400 bool "ThinkPad T400" +config BOARD_LENOVO_T400S + bool "ThinkPad T400s" + config BOARD_LENOVO_T500 bool "ThinkPad T500" diff --git a/src/mainboard/lenovo/t400/Makefile.mk b/src/mainboard/lenovo/t400/Makefile.mk index 982c209..6cd90b4 100644 --- a/src/mainboard/lenovo/t400/Makefile.mk +++ b/src/mainboard/lenovo/t400/Makefile.mk @@ -4,6 +4,7 @@ bootblock-y += dock.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += dock.c ramstage-y += cstates.c @@ -14,5 +15,6 @@ ramstage-$(CONFIG_BOARD_LENOVO_R400) += variants/t400/malibu-3/gma-mainboard.ads ramstage-$(CONFIG_BOARD_LENOVO_T500) += variants/t400/coronado-5/gma-mainboard.ads ramstage-$(CONFIG_BOARD_LENOVO_W500) += variants/t400/coronado-5/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_T400S) += variants/t400/coronado-5/gma-mainboard.ads ramstage-$(CONFIG_BOARD_LENOVO_R500) += variants/r500/gma-mainboard.ads endif diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 259c3e1..fae8892 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -159,32 +159,6 @@ register "bdc_gpio_num" = "48" register "bdc_gpio_lvl" = "0" end - - chip superio/nsc/pc87382 - device pnp 164e.2 off end # IR - device pnp 164e.3 off end # Serial Port - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - device pnp 2e.2 off end # Serial Port / IR - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - end end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 diff --git a/src/mainboard/lenovo/t400/hda_verb.c b/src/mainboard/lenovo/t400/variants/r500/hda_verb.c similarity index 100% copy from src/mainboard/lenovo/t400/hda_verb.c copy to src/mainboard/lenovo/t400/variants/r500/hda_verb.c diff --git a/src/mainboard/lenovo/t400/variants/r500/overridetree.cb b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb index f8291d8..c7b7f50 100644 --- a/src/mainboard/lenovo/t400/variants/r500/overridetree.cb +++ b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb @@ -29,6 +29,30 @@ register "eventa_enable" = "0x83" register "eventb_enable" = "0x00" end + chip superio/nsc/pc87382 + device pnp 164e.2 off end # IR + device pnp 164e.3 off end # Serial Port + device pnp 164e.7 on # GPIO + io 0x60 = 0x1680 + end + device pnp 164e.19 on # DLPC + io 0x60 = 0x164c + end + end + chip superio/nsc/pc87384 + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x3bc + irq 0x70 = 7 + end + device pnp 2e.2 off end # Serial Port / IR + device pnp 2e.3 on # Serial Port + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x1620 + end + end end device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 diff --git a/src/mainboard/lenovo/t400/hda_verb.c b/src/mainboard/lenovo/t400/variants/t400/hda_verb.c similarity index 100% rename from src/mainboard/lenovo/t400/hda_verb.c rename to src/mainboard/lenovo/t400/variants/t400/hda_verb.c diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb index a1b4f9d..d45f04e 100644 --- a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb +++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb @@ -22,6 +22,31 @@ register "has_thinker1" = "0" end + + chip superio/nsc/pc87382 + device pnp 164e.2 off end # IR + device pnp 164e.3 off end # Serial Port + device pnp 164e.7 on # GPIO + io 0x60 = 0x1680 + end + device pnp 164e.19 on # DLPC + io 0x60 = 0x164c + end + end + chip superio/nsc/pc87384 + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x3bc + irq 0x70 = 7 + end + device pnp 2e.2 off end # Serial Port / IR + device pnp 2e.3 on # Serial Port + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x1620 + end + end end device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 diff --git a/src/mainboard/lenovo/t400/variants/t400s/board_info.txt b/src/mainboard/lenovo/t400/variants/t400s/board_info.txt new file mode 100644 index 0000000..c72acb2 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400s/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2009 diff --git a/src/mainboard/lenovo/t400/variants/t400s/data.vbt b/src/mainboard/lenovo/t400/variants/t400s/data.vbt new file mode 100644 index 0000000..f19452d --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t400/variants/t400s/gpio.c b/src/mainboard/lenovo/t400/variants/t400s/gpio.c new file mode 100644 index 0000000..6f0d091 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400s/gpio.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/t400/variants/t400s/hda_verb.c b/src/mainboard/lenovo/t400/variants/t400s/hda_verb.c new file mode 100644 index 0000000..ef60952 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400s/hda_verb.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f15069, // Vendor/Device ID: Conexant CX20585 + 0x17aa2132, // Subsystem ID + 11, + AZALIA_SUBVENDOR(0, 0x17aa2132), + + AZALIA_PIN_CFG(0, 0x19, + AZALIA_PIN_DESC(AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_HP_OUT, AZALIA_STEREO_MONO_1_8, AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, 15, 0)), + AZALIA_PIN_CFG(0, 0x1a, 0x61a190f0), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1b, + AZALIA_PIN_DESC(AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_MIC_IN, AZALIA_STEREO_MONO_1_8, AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, 15, 0)), + AZALIA_PIN_CFG(0, 0x1c, 0x612140f0), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1d, 0x40f001f0), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1f, + AZALIA_PIN_DESC(AZALIA_INTEGRATED, AZALIA_INTERNAL, AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, 15, 0)), + AZALIA_PIN_CFG(0, 0x20, 0x40f001f0), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x23, + AZALIA_PIN_DESC(AZALIA_INTEGRATED, AZALIA_INTERNAL, AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, 15, 0)), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t400/variants/t400s/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400s/overridetree.cb new file mode 100644 index 0000000..9ef5947 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400s/overridetree.cb @@ -0,0 +1,30 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3,4 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0xf" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" + # Set AHCI mode, enable ports 1, 2, 5 (ESATAP), 6 (ESATA). + register "sata_port_map" = "0x33" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic96696921d5a5542a42226c24f7fae253acc4698 Gerrit-Change-Number: 85997 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org>

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[M] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Subrata Banik. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > > Is this just so that socs and mainboards can select this as a default rather than the current OPTI […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:16:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Nicholas Chin. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85905?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in cbfs with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -i option/value -n option_name`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85905/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Nicholas Chin. Subrata Banik has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Is this just so that socs and mainboards can select this as a default rather than the current OPTION_BACKEND_NONE? The CBFS file option backend should always be available since the availability of cbfs files is an integral part of coreboot and can always be manually selected in the config. `USE_CBFS_FILE_OPTION_BACKEND` is part of the choice so, SoC/mainboard won't be able to select `USE_CBFS_FILE_OPTION_BACKEND` directly. Therefore, we need HAVE_CBFS_FILE_OPTION_BACKEND to allow controlling `USE_CBFS_FILE_OPTION_BACKEND`. Later SoC//mainboard can easily select HAVE_CBFS_FILE_OPTION_BACKEND. -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:06:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Subrata Banik. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > you might need to make the below changes to allow option to be picked from soc/mainboard […] Is this just so that socs and mainboards can select this as a default rather than the current OPTION_BACKEND_NONE? The CBFS file option backend should always be available since the availability of cbfs files is an integral part of coreboot and can always be manually selected in the config. -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Jan 2025 06:02:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.1
by agogo (Code Review) 15 Jan '25

15 Jan '25

agogo has uploaded a new patch set (#3). ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.1 ...................................................................... soc/mediatek/mt8196: Add MCUPM firmware v1.1 Change to use release branch TEST=NA BUG=b:317009620 Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Signed-off-by: Agogo Huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mcupm.bin M soc/mediatek/mt8196/mcupm.bin.md5 M soc/mediatek/mt8196/mcupm_release_notes.txt 3 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/85980/3 -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 3 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com>

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