coreboot-gerrit January 2025

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add DDP driver
by Nancy Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Nancy Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add DDP driver ...................................................................... Patch Set 3: (22 comments) File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/86bf8f97_024e6656?us… : PS2, Line 17: clrbits32(&reg->datapath_con, BIT(4)); : setbits32(&reg->datapath_con, BIT(5)); > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/4e8ecabf_3643d45f?us… : PS2, Line 28: break; > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/a11d50f6_fd6bf752?us… : PS2, Line 36: height << 16 | width > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/9b4b9b37_f8ce30d8?us… : PS2, Line 38: ff > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/bd466012_6f2cfdb6?us… : PS2, Line 130: 0xff > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/6fd611f0_b76375c9?us… : PS2, Line 196: /* mutex enable*/ > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/02baabc1_93953a81?us… : PS2, Line 205: blender_config(0, width, height, FIRST_BLENDER); : blender_config(1, width, height, OTHERS); : blender_config(2, width, height, OTHERS); : blender_config(3, width, height, LAST_BLENDER); : blender_start(0); : blender_start(1); : blender_start(2); : blender_start(3); > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/70322f5d_5f1000f2?us… : PS2, Line 233: /* async config*/ > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/7143d5ec_a905df49?us… : PS2, Line 264: /* exdma start*/ > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/3b1131c4_c53523de?us… : PS2, Line 275: 0xffffffff > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/c1da9bef_abaa630e?us… : PS2, Line 308: > Sorry, I think I need to check 13bit for the whole path support […] Done File src/soc/mediatek/mt8196/include/soc/ddp.h: https://review.coreboot.org/c/coreboot/+/85950/comment/6da1a668_1f16699e?us… : PS2, Line 10: #define MAIN_PATH_OVL_NR 2 > OK, I will remove it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/1539154d_1766e3d8?us… : PS2, Line 15: /* 0x000 */ > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/d93658a1_7f50daf0?us… : PS2, Line 58: check_member(ovlsys_cfg, rsz_in_cb2, 0xF70); > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/36bc801f_82d02dfb?us… : PS2, Line 110: 0xc30 > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/41d64ec7_535ed17c?us… : PS2, Line 279: }; > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/93b36fba_0166dca4?us… : PS2, Line 281: (void *)MMSYS_MUTEX_BASE, : (void *)MMSYS1_MUTEX_BASE, : (void *)OVLSYS_MUTEX_BASE, > OK, I will fix it. Done https://review.coreboot.org/c/coreboot/+/85950/comment/87ded2b7_9f4a6202?us… : PS2, Line 286: OVL_INPUT_FORMAT > OK, I will fix it Done https://review.coreboot.org/c/coreboot/+/85950/comment/6a7015b3_524ebec7?us… : PS2, Line 317: /* DISPSYS mutex module*/ > OK, I will fix it Done https://review.coreboot.org/c/coreboot/+/85950/comment/afd2a782_143d4bb8?us… : PS2, Line 343: /* DISPSYS1 mutex module*/ > OK, I will fix it Done https://review.coreboot.org/c/coreboot/+/85950/comment/da87bec9_a39c83a0?us… : PS2, Line 365: OTHERS > OK, I will fix it Done https://review.coreboot.org/c/coreboot/+/85950/comment/b43cabb2_aa6bf88d?us… : PS2, Line 366: BLENDER_LAYER_MAX, > OK, I will fix it Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 09:23:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add DDP driver
by Nancy Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Nancy Lin. Nancy Lin has uploaded a new patch set (#3) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add DDP driver ...................................................................... soc/mediatek/mt8196: Add DDP driver Add DDP (display controller) driver that supports main path to eDP panel. TEST=build pass and firmware display ok BUG=b:343351631 Signed-off-by: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 --- M src/soc/mediatek/common/display.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/ddp.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/ddp.h A src/soc/mediatek/mt8196/include/soc/dsi.h 6 files changed, 808 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/85950/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: Upgrade GCC to 15-20250112 Snapshot
by Elyes Haouas (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Christian Walter, Elyes Haouas, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Upgrade GCC to 15-20250112 Snapshot ...................................................................... Upgrade GCC to 15-20250112 Snapshot And remove unmantained riscv & opensbi Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .gitmodules D 3rdparty/opensbi M MAINTAINERS M Makefile.mk D configs/config.emulation_qemu_riscv_rv64 D configs/config.sifive_hifive-unleashed.opensbi M payloads/Kconfig M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 D payloads/external/LinuxBoot/riscv/defconfig-64 D payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.mk M payloads/external/linux/Kconfig.name D src/arch/riscv/Kconfig D src/arch/riscv/Makefile.mk D src/arch/riscv/arch_timer.c D src/arch/riscv/boot.c D src/arch/riscv/bootblock.S D src/arch/riscv/fit_payload.c D src/arch/riscv/fp_asm.S D src/arch/riscv/include/arch/barrier.h D src/arch/riscv/include/arch/boot.h D src/arch/riscv/include/arch/byteorder.h D src/arch/riscv/include/arch/cache.h D src/arch/riscv/include/arch/cbconfig.h D src/arch/riscv/include/arch/cpu.h D src/arch/riscv/include/arch/encoding.h D src/arch/riscv/include/arch/errno.h D src/arch/riscv/include/arch/exception.h D src/arch/riscv/include/arch/header.ld D src/arch/riscv/include/arch/hlt.h D src/arch/riscv/include/arch/io.h D src/arch/riscv/include/arch/memlayout.h D src/arch/riscv/include/arch/mmio.h D src/arch/riscv/include/arch/pmp.h D src/arch/riscv/include/arch/smp/atomic.h D src/arch/riscv/include/arch/smp/smp.h D src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/bits.h D src/arch/riscv/include/mcall.h D src/arch/riscv/include/sbi.h D src/arch/riscv/include/vm.h D src/arch/riscv/mcall.c D src/arch/riscv/misc.c D src/arch/riscv/opensbi.c D src/arch/riscv/payload.c D src/arch/riscv/pmp.c D src/arch/riscv/ramstage.S D src/arch/riscv/romstage.S D src/arch/riscv/sbi.c D src/arch/riscv/smp.c D src/arch/riscv/tables.c D src/arch/riscv/trap_handler.c D src/arch/riscv/trap_util.S D src/arch/riscv/virtual_memory.c M src/commonlib/bsd/lz4_wrapper.c M src/drivers/uart/Kconfig M src/drivers/uart/Makefile.mk D src/drivers/uart/sifive.c M src/include/acpi/acpi.h M src/include/bootmem.h M src/include/program_loading.h M src/include/rules.h M src/lib/bootmem.c M src/lib/libgcc.c M src/mainboard/emulation/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig.name D src/mainboard/emulation/qemu-riscv/Makefile.mk D src/mainboard/emulation/qemu-riscv/board_info.txt D src/mainboard/emulation/qemu-riscv/cbmem.c D src/mainboard/emulation/qemu-riscv/chip.c D src/mainboard/emulation/qemu-riscv/clint.c D src/mainboard/emulation/qemu-riscv/devicetree.cb D src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h D src/mainboard/emulation/qemu-riscv/mainboard.c D src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/rom_media.c D src/mainboard/emulation/qemu-riscv/romstage.c D src/mainboard/emulation/qemu-riscv/uart.c D src/mainboard/emulation/spike-riscv/Kconfig D src/mainboard/emulation/spike-riscv/Kconfig.name D src/mainboard/emulation/spike-riscv/Makefile.mk D src/mainboard/emulation/spike-riscv/board_info.txt D src/mainboard/emulation/spike-riscv/clint.c D src/mainboard/emulation/spike-riscv/devicetree.cb D src/mainboard/emulation/spike-riscv/mainboard.c D src/mainboard/emulation/spike-riscv/memlayout.ld D src/mainboard/emulation/spike-riscv/rom_media.c D src/mainboard/emulation/spike-riscv/romstage.c D src/mainboard/emulation/spike-riscv/uart.c D src/mainboard/sifive/Kconfig D src/mainboard/sifive/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Kconfig D src/mainboard/sifive/hifive-unleashed/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Makefile.mk D src/mainboard/sifive/hifive-unleashed/board_info.txt D src/mainboard/sifive/hifive-unleashed/devicetree.cb D src/mainboard/sifive/hifive-unleashed/fixup_fdt.c D src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi D src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/mainboard.c D src/mainboard/sifive/hifive-unleashed/media.c D src/mainboard/sifive/hifive-unleashed/romstage.c D src/mainboard/sifive/hifive-unmatched/Kconfig D src/mainboard/sifive/hifive-unmatched/Kconfig.name D src/mainboard/sifive/hifive-unmatched/Makefile.mk D src/mainboard/sifive/hifive-unmatched/board_info.txt D src/mainboard/sifive/hifive-unmatched/cbfs_spi.c D src/mainboard/sifive/hifive-unmatched/devicetree.cb D src/mainboard/sifive/hifive-unmatched/fixup_fdt.c D src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts D src/mainboard/sifive/hifive-unmatched/mainboard.c D src/mainboard/sifive/hifive-unmatched/romstage.c D src/soc/sifive/fu540/Kconfig D src/soc/sifive/fu540/Makefile.mk D src/soc/sifive/fu540/bootblock.c D src/soc/sifive/fu540/cbmem.c D src/soc/sifive/fu540/chip.c D src/soc/sifive/fu540/clint.c D src/soc/sifive/fu540/clock.c D src/soc/sifive/fu540/ddrregs.h D src/soc/sifive/fu540/include/soc/addressmap.h D src/soc/sifive/fu540/include/soc/clock.h D src/soc/sifive/fu540/include/soc/otp.h D src/soc/sifive/fu540/include/soc/sdram.h D src/soc/sifive/fu540/include/soc/spi.h D src/soc/sifive/fu540/memlayout.ld D src/soc/sifive/fu540/otp.c D src/soc/sifive/fu540/regconfig-ctl.h D src/soc/sifive/fu540/regconfig-phy.h D src/soc/sifive/fu540/sdram.c D src/soc/sifive/fu540/spi.c D src/soc/sifive/fu540/spi_internal.h D src/soc/sifive/fu540/uart.c D src/soc/sifive/fu540/ux00ddr.h D src/soc/sifive/fu740/Kconfig D src/soc/sifive/fu740/Makefile.mk D src/soc/sifive/fu740/TODO D src/soc/sifive/fu740/cbmem.c D src/soc/sifive/fu740/chip.c D src/soc/sifive/fu740/clint.c D src/soc/sifive/fu740/clock.c D src/soc/sifive/fu740/ddrregs.c D src/soc/sifive/fu740/gpio.c D src/soc/sifive/fu740/include/soc/addressmap.h D src/soc/sifive/fu740/include/soc/clock.h D src/soc/sifive/fu740/include/soc/gpio.h D src/soc/sifive/fu740/include/soc/otp.h D src/soc/sifive/fu740/include/soc/sdram.h D src/soc/sifive/fu740/include/soc/spi.h D src/soc/sifive/fu740/memlayout.ld D src/soc/sifive/fu740/otp.c D src/soc/sifive/fu740/sdram.c D src/soc/sifive/fu740/spi.c D src/soc/sifive/fu740/spi_internal.h D src/soc/sifive/fu740/uart.c D src/soc/ucb/riscv/Kconfig D src/soc/ucb/riscv/Makefile.mk D src/soc/ucb/riscv/cbmem.c D src/soc/ucb/riscv/chip.c M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-15-20250112_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20250112_gnat.patch R util/crossgcc/patches/gcc-15-20250112_libcpp.patch R util/crossgcc/patches/gcc-15-20250112_libgcc.patch R util/crossgcc/patches/gcc-15-20250112_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20250112_rv32iafc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20250112.tar.xz.cksum D util/riscv/description.md D util/riscv/make-spike-elf.sh D util/riscv/sifive-gpt.py D util/riscv/spike-elf.ld 179 files changed, 57 insertions(+), 13,590 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'
by Felix Singer (Code Review) 15 Jan '25

15 Jan '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85785?usp=email ) Change subject: samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long' ...................................................................... samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Change-Id: I7eddb0934ccd24c9994a60d7058a1e518c6c9c9f Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85785 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5250/include/soc/dp-core.h 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index ab097e2..2ddc49c 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -95,7 +95,7 @@ * @param lcdbase pointer to the base address of framebuffer. * @param pd pointer to the main panel_data structure */ -void fb_init(unsigned long int fb_size, void *lcdbase, +void fb_init(unsigned long fb_size, void *lcdbase, struct exynos5_fimd_panel *pd) { unsigned int val; @@ -532,7 +532,7 @@ * @param lcdbase Base address of LCD frame buffer * @return 0 if ok, -ve error code on error */ -int lcd_ctrl_init(unsigned long int fb_size, +int lcd_ctrl_init(unsigned long fb_size, struct exynos5_fimd_panel *panel_data, void *lcdbase) { int ret = 0; diff --git a/src/soc/samsung/exynos5250/include/soc/dp-core.h b/src/soc/samsung/exynos5250/include/soc/dp-core.h index 0c8aed7..6b2a21c 100644 --- a/src/soc/samsung/exynos5250/include/soc/dp-core.h +++ b/src/soc/samsung/exynos5250/include/soc/dp-core.h @@ -234,9 +234,9 @@ /* startup and init */ struct exynos5_fimd_panel; -void fb_init(unsigned long int fb_size, void *lcdbase, +void fb_init(unsigned long fb_size, void *lcdbase, struct exynos5_fimd_panel *pd); int dp_controller_init(struct s5p_dp_device *dp_device); -int lcd_ctrl_init(unsigned long int fb_size, +int lcd_ctrl_init(unsigned long fb_size, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* CPU_SAMSUNG_EXYNOS5250_DP_CORE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7eddb0934ccd24c9994a60d7058a1e518c6c9c9f Gerrit-Change-Number: 85785 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'
by Felix Singer (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Ariel Otilibili. Felix Singer has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85785?usp=email ) Change subject: samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7eddb0934ccd24c9994a60d7058a1e518c6c9c9f Gerrit-Change-Number: 85785 Gerrit-PatchSet: 2 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 15 Jan 2025 08:32:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/lint: Clear syntax warnings in Python 3.12
by Felix Singer (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Ariel Otilibili. Felix Singer has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85771?usp=email ) Change subject: util/lint: Clear syntax warnings in Python 3.12 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Gerrit-Change-Number: 85771 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 15 Jan 2025 08:30:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/lint: Clear syntax warnings in Python 3.12
by Felix Singer (Code Review) 15 Jan '25

15 Jan '25

Felix Singer has uploaded a new patch set (#3) to the change originally created by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85771?usp=email ) Change subject: util/lint: Clear syntax warnings in Python 3.12 ...................................................................... util/lint: Clear syntax warnings in Python 3.12 Since Python 3.12, invalid escape sequences produce a SyntaxWarning; in the future, they will produce SyntaxError. Using raw strings clear out the warning. Below the command used for checking the fix worked. ``` $ python3 util/lint/checkpatch_json.py ``` Link: https://docs.python.org/3.12/whatsnew/3.12.html#other-language-changes Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> --- M util/lint/checkpatch_json.py 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85771/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Gerrit-Change-Number: 85771 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/nissa: Create dirks variant
by Dinesh Gehlot (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: David Wu, Ivy Jian, Jayvik Desai, Nick Vaccaro. Dinesh Gehlot has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85947?usp=email ) Change subject: mb/google/nissa: Create dirks variant ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57ffb6025ee2115fa558668dc685a1970fc738d0 Gerrit-Change-Number: 85947 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Jan 2025 08:24:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/dirks: Add GPIO table
by Dinesh Gehlot (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: David Wu, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/85975?usp=email ) Change subject: mb/google/nissa/var/dirks: Add GPIO table ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85975?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e3bc60a1c749b65c542a74eb6167e921ef369f2 Gerrit-Change-Number: 85975 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Jan 2025 08:23:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat
by Subrata Banik (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jayvik Desai, Kapil Porwal. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85999?usp=email ) Change subject: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Gerrit-Change-Number: 85999 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 08:18:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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