coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/google/rauru: Run mtk-fsp in romstage
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86015?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Run mtk-fsp in romstage ...................................................................... mb/google/rauru: Run mtk-fsp in romstage Run mtk_fsp_romstage.elf (MediaTek firmware support package for romstage) in romstage to support power switch. BUG=b:373797027 TEST=build pass, boot ok. Load and run mtk_fsp with following logs: [DEBUG] FMAP: area FW_MAIN_A found @ 402000 (1527552 bytes) [INFO ] CBFS: Found 'fallback/mtk_fsp_romstage' @0xfc280 size 0x6bd in mcache @0x00122518 [INFO ] VB2:vb2_digest_init() 1725 bytes, hash algo 2, HW acceleration enabled [INFO ] _start: MediaTek FSP_ROMSTAGE interface version: 1.0 [INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase 0x30 done Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86015 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index d82e152..32c8a61 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -9,6 +9,7 @@ #include <soc/mt6363.h> #include <soc/mt6373.h> #include <soc/mt6685.h> +#include <soc/mtk_fsp.h> #include <soc/mtk_pwrsel.h> #include <soc/pcie.h> #include <soc/pll.h> @@ -34,6 +35,8 @@ mt6316_init(); raise_little_cpu_freq(); mt6373_init(); + mtk_fsp_init(ROMSTAGE_INIT); + mtk_fsp_load_and_run(); mt6685_init(); srclken_rc_init(); clk_buf_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Gerrit-Change-Number: 86015 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86014?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in romstage ...................................................................... soc/mediatek/mt8196: Add mtk-fsp loader in romstage Reserve 64KB memory at 0x02140000 for mtk_fsp_romstage.elf. BUG=b:373797027 TEST=build pass Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86014 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/memlayout.ld 3 files changed, 12 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h index 9e5f11b..5bb5c38 100644 --- a/src/soc/mediatek/common/include/soc/memlayout.h +++ b/src/soc/mediatek/common/include/soc/memlayout.h @@ -18,6 +18,9 @@ _ = ASSERT(size % 4K == 0, \ "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#define FSP_ROMSTAGE_INIT_CODE(addr, size) \ + REGION(fsp_romstage_init_code, addr, size, 64K) + #define FSP_RAMSTAGE_INIT_CODE(addr, size) \ REGION(fsp_ramstage_init_code, addr, size, 64K) diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 84bf3b6..80dac20 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -97,6 +97,14 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(DRAM_CBFS) +FSP_ROMSTAGE_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_romstage +$(FSP_ROMSTAGE_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_romstage.elf +$(FSP_ROMSTAGE_CBFS)-type := stage +$(FSP_ROMSTAGE_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(FSP_ROMSTAGE_CBFS)-file)),) +cbfs-files-y += $(FSP_ROMSTAGE_CBFS) +endif + FSP_RAMSTAGE_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage $(FSP_RAMSTAGE_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_ramstage.elf $(FSP_RAMSTAGE_CBFS)-type := stage diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 6c35a47..74f1543 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -57,6 +57,7 @@ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) PRERAM_CBFS_CACHE(0x020DA000, 48K) PRERAM_CBMEM_CONSOLE(0x020E6000, 340K) + FSP_ROMSTAGE_INIT_CODE(0x02140000, 64K) SRAM_L2C_END(0x02200000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/86014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Gerrit-Change-Number: 86014 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... soc/mediatek/mt8196: Add mtk-fsp loader in ramstage MediaTek firmware support package (mtk-fsp) contains romstage and ramstage blobs. Add support for the ramstage blob, which includes: - UFS mphy settings. - DPAC (Device Access Permission Control) settings. - MMinfra (Multimedia Infrastrucutre) settings. - SMPU (Security Memory Protection Unit) settings. - Advanced CPU frequency control. BUG=b:373797027 TEST=build pass, boot ok. Load and run mtk_fsp with following logs: [INFO ] CBFS: Found 'fallback/mtk_fsp_ramstage' @0xfca00 size 0x263d in mcache @0xfffdd5a0 [DEBUG] read SPI 0x4fea88 0x263d: 773 us, 12663 KB/s, 101.304 Mbps [INFO ] VB2:vb2_digest_init() 9789 bytes, hash algo 2, HW acceleration enabled [INFO ] _start: MediaTek FSP_RAMSTAGE interface version: 1.0 [INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 done Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86013 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/common/include/soc/mtk_fsp_common.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 5 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h index f51c2a1..9e5f11b 100644 --- a/src/soc/mediatek/common/include/soc/memlayout.h +++ b/src/soc/mediatek/common/include/soc/memlayout.h @@ -18,5 +18,8 @@ _ = ASSERT(size % 4K == 0, \ "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#define FSP_RAMSTAGE_INIT_CODE(addr, size) \ + REGION(fsp_ramstage_init_code, addr, size, 64K) + #define EARLY_INIT(addr, size) \ REGION(early_init_data, addr, size, 4) diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h index ea3d46f..99453ba 100644 --- a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -33,6 +33,7 @@ FSP_PARAM_TYPE_INVALID = 0, /* 0x40000000+ reserved for input type params */ FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN), + FSP_PARAM_TYPE_STORAGE, /* 0x80000000+ reserved for output type params */ FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT), diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 073f67e..84bf3b6 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -97,6 +97,14 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(DRAM_CBFS) +FSP_RAMSTAGE_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage +$(FSP_RAMSTAGE_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_ramstage.elf +$(FSP_RAMSTAGE_CBFS)-type := stage +$(FSP_RAMSTAGE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +ifneq ($(wildcard $($(FSP_RAMSTAGE_CBFS)-file)),) +cbfs-files-y += $(FSP_RAMSTAGE_CBFS) +endif + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@ diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index f8ee114..6c35a47 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -64,6 +64,7 @@ POSTRAM_CBFS_CACHE(0x80100000, 2M) RAMSTAGE(0x80300000, 2M) OPTEE_BUF(0x80500000, 70M) + FSP_RAMSTAGE_INIT_CODE(0x90000000, 2M) BL31(0x94600000, 0x200000) diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 1f1da7c..1636f29 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -8,8 +8,10 @@ #include <soc/gpueb.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> +#include <soc/mtk_fsp.h> #include <soc/pcie.h> #include <soc/sspm.h> +#include <soc/storage.h> #include <soc/symbols.h> #include <symbols.h> @@ -33,6 +35,11 @@ static void soc_init(struct device *dev) { + mtk_fsp_init(RAMSTAGE_SOC_INIT); + uint32_t storage_type = mainboard_get_storage_type(); + mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type); + mtk_fsp_load_and_run(); + mtk_mmu_disable_l2c_sram(); sspm_init(); gpueb_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek: Allow specifying multiple EINT base registers
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86033?usp=email ) Change subject: soc/mediatek: Allow specifying multiple EINT base registers ...................................................................... soc/mediatek: Allow specifying multiple EINT base registers Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers, each with a different number of EINT bits. In preparation for the upcoming MT8196 EINT unmasking support, replace the `eint_event_reg` struct (which has a hardcoded register number) with an array `eint_event` to specify the EINT base register(s). BUG=none TEST=emerge-geralt coreboot BRANCH=none Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86033 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/eint_event.c A src/soc/mediatek/common/eint_event_info.c M src/soc/mediatek/common/include/soc/eint_event.h M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8192/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 7 files changed, 44 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/eint_event.c b/src/soc/mediatek/common/eint_event.c index b3538a1..6e44b37 100644 --- a/src/soc/mediatek/common/eint_event.c +++ b/src/soc/mediatek/common/eint_event.c @@ -1,10 +1,30 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> +#include <device/mmio.h> #include <soc/eint_event.h> +#include <types.h> + +/* EINT reg_base + 0x880 is eint_event_mask_clr register with access type W1C. */ +#define EINT_EVENT_MASK_CLR_OFFSET 0x880 + +#define EINT_VALUE 0xFFFFFFFF + +static void enable_eint_event(const struct eint_event_info *event) +{ + uint32_t *reg = (uint32_t *)(event->reg_base + EINT_EVENT_MASK_CLR_OFFSET); + size_t port = DIV_ROUND_UP(event->eint_num, sizeof(*reg) * BITS_PER_BYTE); + int i; + + for (i = 0; i < port; i++) + write32p(reg[i], EINT_VALUE); +} void unmask_eint_event_mask(void) { - int i; - for (i = 0; i < ARRAY_SIZE(mtk_eint_event->eint_event_mask_clr); i++) - write32(&mtk_eint_event->eint_event_mask_clr[i], 0xffffffff); + const struct eint_event_info *event = &eint_event[0]; + while (event->reg_base && event->eint_num) { + enable_eint_event(event); + event++; + } } diff --git a/src/soc/mediatek/common/eint_event_info.c b/src/soc/mediatek/common/eint_event_info.c new file mode 100644 index 0000000..706cca8 --- /dev/null +++ b/src/soc/mediatek/common/eint_event_info.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/addressmap.h> +#include <soc/eint_event.h> + +const struct eint_event_info eint_event[] = { + { EINT_BASE, 224 }, + {}, +}; diff --git a/src/soc/mediatek/common/include/soc/eint_event.h b/src/soc/mediatek/common/include/soc/eint_event.h index 6d544b4..eab51ed 100644 --- a/src/soc/mediatek/common/include/soc/eint_event.h +++ b/src/soc/mediatek/common/include/soc/eint_event.h @@ -3,18 +3,18 @@ #ifndef SOC_MEDIATEK_COMMON_EINT_EVENT_H #define SOC_MEDIATEK_COMMON_EINT_EVENT_H -#include <device/mmio.h> -#include <soc/addressmap.h> +#include <stddef.h> +#include <stdint.h> -/* eint event mask clear register */ -struct eint_event_reg { - uint32_t eint_event_mask_clr[7]; +struct eint_event_info { + uintptr_t reg_base; + size_t eint_num; }; -/* eint_base + 0x880 is eint_event_mask_clr register with access type W1C. */ -static struct eint_event_reg *const mtk_eint_event = (void *)(EINT_BASE + 0x880); +/* An element { 0, 0 } indicates the end of array. */ +extern const struct eint_event_info eint_event[]; -/* unmask eint event, eint can wakeup by spm */ +/* Unmask eint event, which can be waken up by SPM. */ void unmask_eint_event_mask(void); #endif diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk index 0d44c2e..c4a3f21 100644 --- a/src/soc/mediatek/mt8186/Makefile.mk +++ b/src/soc/mediatek/mt8186/Makefile.mk @@ -12,7 +12,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += gic.c bootblock-y += ../common/lastbus_v1.c bootblock-y += ../common/mmu_operations.c diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index 2f1a0f5..2c8379e 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -10,7 +10,7 @@ all-y += ../common/uart.c bootblock-y += ../common/bootblock.c bootblock.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk index 1c4baa8..b2c3ced 100644 --- a/src/soc/mediatek/mt8192/Makefile.mk +++ b/src/soc/mediatek/mt8192/Makefile.mk @@ -10,7 +10,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 7c3d3f4..ecc6965 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -11,7 +11,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/early_init.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/pll.c pll.c -- To view, visit https://review.coreboot.org/c/coreboot/+/86033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba Gerrit-Change-Number: 86033 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Shunxi Zhang. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/a4e2d341_46ac0fe4?us… : PS2, Line 193: RTC_CON_GPU > I think the original indent was correct? You are right. I did not see there is `)` on above. @jarried.lin@mediatek.com please revert to original indent. -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 12:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 12:33:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86035?usp=email ) Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 12:32:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

1 0

[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Shunxi Zhang, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 3: (17 comments) File src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/2dbbde36_6b558ea3?us… : PS2, Line 84: /* : * Complete the RTC initialization process, : * setting of related registers : */ > `/* Complete the RTC initialization process and register settings. […] Done File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/ef52f750_a4bae687?us… : PS2, Line 58: WATCH_INIT > If this means "stopwatch_init", please use a more descriptive name. […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/bcd876da_3f60e4e4?us… : PS2, Line 59: WAIT_EOSC_CHECK_CLK_RDY_TIME_US > `EOSC_CHECK_CLK_TIMEOUT_US` Done https://review.coreboot.org/c/coreboot/+/85978/comment/caa7f056_d411e1d1?us… : PS2, Line 60: RETRY_MAX_TIME > `RECOVERY_RETRY_COUNT` Done File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/2e40a3d3_b702faba?us… : PS1, Line 68: RG_BANK_FQMTR_RST_SHIFT); > keep comment unresolved Done File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/38205d9d_363fa134?us… : PS2, Line 101: ERROR: get frequency > `FQMTR read` Done https://review.coreboot.org/c/coreboot/+/85978/comment/c5117fee_9aef9309?us… : PS2, Line 105: 26M/32K = 794 > `26MHz / 23K = (26 * 10^6) / (23 * 1024) ~= 794` Done https://review.coreboot.org/c/coreboot/+/85978/comment/12c11481_9abac1a2?us… : PS2, Line 139: > You removed the wrong blank line. […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/316f9b0d_d4e716b4?us… : PS2, Line 325: rtc_powerkey_init(); : : if (!rtc_write_trigger()) : return false; > `rtc_powerkey_init` already contains `rtc_write_trigger`. Change this to […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/71d3a3dc_b3340d73?us… : PS2, Line 340: rtc_powerkey_init(); : if (!rtc_write_trigger()) : return false; > ``` […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/2289d520_fe91b100?us… : PS2, Line 375: wrritten > written Done https://review.coreboot.org/c/coreboot/+/85978/comment/b3270035_20413460?us… : PS2, Line 391: wrritten > written Done https://review.coreboot.org/c/coreboot/+/85978/comment/6bffbfce_c4a1fbec?us… : PS2, Line 414: need > `needs to` Done https://review.coreboot.org/c/coreboot/+/85978/comment/7734fbff_c260fc75?us… : PS2, Line 415: rtc_powerkey_init(); : : if (!rtc_write_trigger()) { > `if (!rtc_powerkey_init()) {` Done https://review.coreboot.org/c/coreboot/+/85978/comment/d7963f44_7b324dbd?us… : PS2, Line 419: rtc_write_trigger > `rtc_powerkey_init failed` Done https://review.coreboot.org/c/coreboot/+/85978/comment/d71f07df_c4ecd283?us… : PS2, Line 425: > failed Done https://review.coreboot.org/c/coreboot/+/85978/comment/aafd67ea_70c893d0?us… : PS2, Line 504: Check clock source are match with 32K exist > `Check if clock sources match existing 32K` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 12:28:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86034?usp=email ) Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a7c0d2fa1f93a55731b4b58923d6f80a4c4be89 Gerrit-Change-Number: 86034 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 12:21:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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