coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86008?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD ...................................................................... mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD Enables onboard LEDs for power and reset button as well as flash chip indicator LED. Also enables POST code display. Both LEDs and PCD turn on when the system is powered and turn off once the payload is reached. This mimics the behavior on vendor firmware. Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86008 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c M src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb A src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c A src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c 4 files changed, 134 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c index 1cec5c4..2025022 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c +++ b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c @@ -1,8 +1,46 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> #include <southbridge/intel/lynxpoint/pch.h> -/* FIXME: remove this if not needed */ +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + void mainboard_config_superio(void) { + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x4e); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power on the status LEDs */ + pnp_set_logical_device(GPIO1_ENABLE_DEV); + pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1); + + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0xf0, 0x30); + pnp_write_config(GPIO1_DEV, 0xf1, 0x31); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index c1acd5c..6077176 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -98,8 +98,10 @@ device pnp 2e.107 off end # GPIO9 device pnp 2e.8 off end # WDT device pnp 2e.108 on # GPIO0 - irq 0xe0 = 0xf9 # + GPIO0 direction - irq 0xe1 = 0xfd # + GPIO0 value + irq 0xe0 = 0xff # + GPIO0 direction + irq 0xe1 = 0x00 # + GPIO0 value + irq 0xf0 = 0x30 # + GPIO1 direction + irq 0xf1 = 0x31 # + GPIO1 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c new file mode 100644 index 0000000..1e62d65 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ +#include <arch/io.h> +#include <bootstate.h> +#include <device/device.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void turn_off_leds(void *unused) +{ + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0x27, 0xd0); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, turn_off_leds, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, turn_off_leds, NULL); diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c new file mode 100644 index 0000000..6736c15 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Cut off power to LEDs when system goes to sleep. + */ + if (slp_typ >= ACPI_S3) { + + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7 Gerrit-Change-Number: 86008 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... mb/asrock/fatal1ty_z87_professional: List another USB debug port List an additional USB debug port on one of the USB-2.0-Headers. Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86007 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/fatal1ty_z87_professional/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Angel Pons: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig index b1600ef..c83a900 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig +++ b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig @@ -22,5 +22,5 @@ default "Fatal1ty Z87 Professional" config USBDEBUG_HCD_INDEX - default 2 # USB-2.0-Header with the designation USB4_5 + default 2 # Headers: USB45, USB3_6_7 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 4 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Update devicetree
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86006?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Update devicetree ...................................................................... mb/asrock/fatal1ty_z87_professional: Update devicetree Add various previously missing settings as well as a few devices, also tidy up the comments and make whitespace consistent. Tested on hardware, no regressions were observed. Mainboard boots Arch Linux with EDKII payload, S3 suspend and resume works, as before. Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86006 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb 1 file changed, 35 insertions(+), 26 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index 5b20f3c..c1acd5c 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -1,4 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + chip northbridge/intel/haswell + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on @@ -8,18 +12,20 @@ device domain 0 on ops haswell_pci_domain_ops - device pci 00.0 on # Desktop Host bridge + device pci 00.0 on # Desktop Host bridge subsystemid 0x1849 0x0c00 end - device pci 01.0 on # PEG + device pci 01.0 on # PCIE2 subsystemid 0x1849 0x0c01 end - device pci 01.1 on end - device pci 01.2 on end - device pci 02.0 on # iGPU + device pci 01.1 on # PCIE3 + end + device pci 01.2 on # PCIE4 + end + device pci 02.0 on # iGPU subsystemid 0x1849 0x0412 end - device pci 03.0 on # Mini-HD audio + device pci 03.0 on # Mini-HD audio subsystemid 0x1849 0x0c0c end @@ -27,48 +33,51 @@ register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" register "sata_port_map" = "0x3f" - device pci 14.0 on # xHCI Controller + device pci 14.0 on # xHCI Controller subsystemid 0x1849 0x8c31 end - device pci 16.0 on # MEI #1 + device pci 16.0 on # MEI #1 subsystemid 0x1849 0x8c3a end - device pci 16.1 off end # MEI #2 - device pci 19.0 on # Intel Gigabit Ethernet + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet subsystemid 0x1849 0x153b end - device pci 1a.0 on # USB2 EHCI #2 + device pci 1a.0 on # USB2 EHCI #2 subsystemid 0x1849 0x8c2d end - device pci 1b.0 on # High Definition Audio + device pci 1b.0 on # High Definition Audio subsystemid 0x1849 0x1020 end - device pci 1c.0 off end # RP #1 - device pci 1c.1 on # RP #2: mPCIe slot + device pci 1c.0 off end # RP #1 + device pci 1c.1 on # RP #2: mPCIe slot subsystemid 0x1849 0x8c12 end - device pci 1c.2 on # RP #3: ASM1061 SATA controller + device pci 1c.2 on # RP #3: ASM1061 SATA controller subsystemid 0x1849 0x8c14 end - device pci 1c.3 on # RP #4: Intel I211 GbE + device pci 1c.3 on # RP #4: Intel I211 GbE subsystemid 0x1849 0x8c16 device pci 00.0 on end end - device pci 1c.4 on # RP #5: ASM1061 SATA controller + device pci 1c.4 on # RP #5: ASM1061 SATA controller subsystemid 0x1849 0x8c18 end - device pci 1c.5 on # RP #6: PCIe x1 slot + device pci 1c.5 on # RP #6: PCIE1 subsystemid 0x1849 0x8c1a end - device pci 1c.6 on # RP #7: ASM1083 PCIe-to-PCI bridge + device pci 1c.6 on # RP #7: ASM1083 PCIe-to-PCI bridge subsystemid 0x1849 0x8c1c end - device pci 1c.7 off end # RP #8 - device pci 1d.0 on # USB2 EHCI #1 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x1849 0x8c26 end - device pci 1f.0 on # LPC bridge + device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x8c44 chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -123,12 +132,12 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA Controller (AHCI) - device pci 1f.3 on # SMBus + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on # SMBus subsystemid 0x1849 0x8c22 end - device pci 1f.5 off end # SATA Controller (Legacy) - device pci 1f.6 off end # Thermal + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44 Gerrit-Change-Number: 86006 Gerrit-PatchSet: 6 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87M Extreme4 (Haswell)
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85884?usp=email ) Change subject: mb/asrock: Add Z87M Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87M Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - All four rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots - PCI Express 2.0 x16 slot - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) tested: - IR header - COM Port header - eSATA connector - PS/2 Mouse/Keyboard Port Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85884 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/asrock/z87m_extreme4/Kconfig A src/mainboard/asrock/z87m_extreme4/Kconfig.name A src/mainboard/asrock/z87m_extreme4/Makefile.mk A src/mainboard/asrock/z87m_extreme4/acpi/ec.asl A src/mainboard/asrock/z87m_extreme4/acpi/platform.asl A src/mainboard/asrock/z87m_extreme4/acpi/superio.asl A src/mainboard/asrock/z87m_extreme4/board_info.txt A src/mainboard/asrock/z87m_extreme4/bootblock.c A src/mainboard/asrock/z87m_extreme4/data.vbt A src/mainboard/asrock/z87m_extreme4/devicetree.cb A src/mainboard/asrock/z87m_extreme4/dsdt.asl A src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87m_extreme4/gpio.c A src/mainboard/asrock/z87m_extreme4/hda_verb.c A src/mainboard/asrock/z87m_extreme4/romstage.c 15 files changed, 520 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/asrock/z87m_extreme4/Kconfig b/src/mainboard/asrock/z87m_extreme4/Kconfig new file mode 100644 index 0000000..e02ac39 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87M_EXTREME4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87m_extreme4" + +config MAINBOARD_PART_NUMBER + default "Z87M Extreme4" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: LAN_USB3_23 (Upper) + # Header: USB4_5 +endif diff --git a/src/mainboard/asrock/z87m_extreme4/Kconfig.name b/src/mainboard/asrock/z87m_extreme4/Kconfig.name new file mode 100644 index 0000000..7f8d11a --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87M_EXTREME4 + bool "Z87M Extreme4" diff --git a/src/mainboard/asrock/z87m_extreme4/Makefile.mk b/src/mainboard/asrock/z87m_extreme4/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87m_extreme4/acpi/ec.asl b/src/mainboard/asrock/z87m_extreme4/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_extreme4/acpi/platform.asl b/src/mainboard/asrock/z87m_extreme4/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87m_extreme4/acpi/superio.asl b/src/mainboard/asrock/z87m_extreme4/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_extreme4/board_info.txt b/src/mainboard/asrock/z87m_extreme4/board_info.txt new file mode 100644 index 0000000..152a36e --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87M%20Extreme4/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87m_extreme4/bootblock.c b/src/mainboard/asrock/z87m_extreme4/bootblock.c new file mode 100644 index 0000000..7a6607c --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87m_extreme4/data.vbt b/src/mainboard/asrock/z87m_extreme4/data.vbt new file mode 100644 index 0000000..9a0eeb1 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87m_extreme4/devicetree.cb b/src/mainboard/asrock/z87m_extreme4/devicetree.cb new file mode 100644 index 0000000..4e3b335 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/devicetree.cb @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PCIE1 + subsystemid 0x1849 0x0c01 + end + device pci 01.1 on # PCIE3 + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4: PCIE2 x1 slot + subsystemid 0x1849 0x8c16 + end + device pci 1c.4 on # RP #5: PCIE4 + end + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87m_extreme4/dsdt.asl b/src/mainboard/asrock/z87m_extreme4/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads new file mode 100644 index 0000000..8db057d --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- D-Sub + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87m_extreme4/gpio.c b/src/mainboard/asrock/z87m_extreme4/gpio.c new file mode 100644 index 0000000..9f1960f --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87m_extreme4/hda_verb.c b/src/mainboard/asrock/z87m_extreme4/hda_verb.c new file mode 100644 index 0000000..912961c --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87m_extreme4/romstage.c b/src/mainboard/asrock/z87m_extreme4/romstage.c new file mode 100644 index 0000000..2353dd7 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1 Gerrit-Change-Number: 85884 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84672?usp=email ) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Special thanks to Angel for enabling various LEDs/PCD functions! Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - HDMI-Out Port - DVI-D Port - RJ-45 Gigabit LAN Port - Both USB 2.0 Ports - All four USB 3.1 Gen1 Ports - All three USB 2.0 headers - Both USB 3.1 Gen1 headers - Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH) - All six SATA3 6.0 Gb/s connectors by Intel - All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 (fix will soon be merged) not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84672 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/asrock/z87_extreme4/Kconfig A src/mainboard/asrock/z87_extreme4/Kconfig.name A src/mainboard/asrock/z87_extreme4/Makefile.mk A src/mainboard/asrock/z87_extreme4/acpi/ec.asl A src/mainboard/asrock/z87_extreme4/acpi/platform.asl A src/mainboard/asrock/z87_extreme4/acpi/superio.asl A src/mainboard/asrock/z87_extreme4/board_info.txt A src/mainboard/asrock/z87_extreme4/bootblock.c A src/mainboard/asrock/z87_extreme4/data.vbt A src/mainboard/asrock/z87_extreme4/devicetree.cb A src/mainboard/asrock/z87_extreme4/dsdt.asl A src/mainboard/asrock/z87_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87_extreme4/gpio.c A src/mainboard/asrock/z87_extreme4/hda_verb.c A src/mainboard/asrock/z87_extreme4/mainboard.c A src/mainboard/asrock/z87_extreme4/romstage.c A src/mainboard/asrock/z87_extreme4/smihandler.c 17 files changed, 640 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/z87_extreme4/Kconfig b/src/mainboard/asrock/z87_extreme4/Kconfig new file mode 100644 index 0000000..3ef4afa --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_EXTREME4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_extreme4" + +config MAINBOARD_PART_NUMBER + default "Z87 Extreme4" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB3_23 (Upper) + # Header: USB2_3 +endif diff --git a/src/mainboard/asrock/z87_extreme4/Kconfig.name b/src/mainboard/asrock/z87_extreme4/Kconfig.name new file mode 100644 index 0000000..65c3e2f --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_EXTREME4 + bool "Z87 Extreme4" diff --git a/src/mainboard/asrock/z87_extreme4/Makefile.mk b/src/mainboard/asrock/z87_extreme4/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_extreme4/acpi/ec.asl b/src/mainboard/asrock/z87_extreme4/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme4/acpi/platform.asl b/src/mainboard/asrock/z87_extreme4/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_extreme4/acpi/superio.asl b/src/mainboard/asrock/z87_extreme4/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme4/board_info.txt b/src/mainboard/asrock/z87_extreme4/board_info.txt new file mode 100644 index 0000000..a9a7e67 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Extreme4/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_extreme4/bootblock.c b/src/mainboard/asrock/z87_extreme4/bootblock.c new file mode 100644 index 0000000..3d3da8e --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/bootblock.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x48); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power on the status LEDs */ + pnp_set_logical_device(GPIO1_ENABLE_DEV); + pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1); + + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0xf0, 0x30); + pnp_write_config(GPIO1_DEV, 0xf1, 0x31); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_extreme4/data.vbt b/src/mainboard/asrock/z87_extreme4/data.vbt new file mode 100644 index 0000000..e973acc --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87_extreme4/devicetree.cb b/src/mainboard/asrock/z87_extreme4/devicetree.cb new file mode 100644 index 0000000..3e1ed1c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/devicetree.cb @@ -0,0 +1,143 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PCIE2 + end + device pci 01.1 on # PCIE4 + end + device pci 01.2 on # PCIE5 + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3: ASM1061 Serial ATA Controller + subsystemid 0x1849 0x8c14 + end + device pci 1c.3 off end # RP #4 + device pci 1c.4 on # RP #5: PCIE3 x1 Slot + subsystemid 0x1849 0x8c18 + end + device pci 1c.5 on # RP #6: PCIE1 x1 Slot + subsystemid 0x1849 0x8c1a + end + device pci 1c.6 on # RP #7: ASM1083/1085 PCIe to PCI Bridge + subsystemid 0x1849 0x8c1c + end + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xff # + GPIO0 direction + irq 0xe1 = 0x00 # + GPIO0 value + irq 0xf0 = 0x30 # + GPIO1 direction + irq 0xf1 = 0x31 # + GPIO1 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87_extreme4/dsdt.asl b/src/mainboard/asrock/z87_extreme4/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z87_extreme4/gma-mainboard.ads new file mode 100644 index 0000000..c0b52b2 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DP + HDMI1, -- DVI-D + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- D-SUB + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_extreme4/gpio.c b/src/mainboard/asrock/z87_extreme4/gpio.c new file mode 100644 index 0000000..bca2aac --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_extreme4/hda_verb.c b/src/mainboard/asrock/z87_extreme4/hda_verb.c new file mode 100644 index 0000000..ab7da86 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_extreme4/mainboard.c b/src/mainboard/asrock/z87_extreme4/mainboard.c new file mode 100644 index 0000000..1e62d65 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/mainboard.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ +#include <arch/io.h> +#include <bootstate.h> +#include <device/device.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void turn_off_leds(void *unused) +{ + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0x27, 0xd0); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, turn_off_leds, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, turn_off_leds, NULL); diff --git a/src/mainboard/asrock/z87_extreme4/romstage.c b/src/mainboard/asrock/z87_extreme4/romstage.c new file mode 100644 index 0000000..d52bc82 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asrock/z87_extreme4/smihandler.c b/src/mainboard/asrock/z87_extreme4/smihandler.c new file mode 100644 index 0000000..d6ebcef --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/smihandler.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Cut off power to LEDs when system goes to sleep. + */ + if (slp_typ >= ACPI_S3) { + + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 12 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85926?usp=email ) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme3 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - Both rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU) - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) tested: - PCI slots - IR header - COM Port header - PS/2 Mouse/Keyboard Port - Optical SPDIF Out Port Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85926 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/asrock/z87_extreme3/Kconfig A src/mainboard/asrock/z87_extreme3/Kconfig.name A src/mainboard/asrock/z87_extreme3/Makefile.mk A src/mainboard/asrock/z87_extreme3/acpi/ec.asl A src/mainboard/asrock/z87_extreme3/acpi/platform.asl A src/mainboard/asrock/z87_extreme3/acpi/superio.asl A src/mainboard/asrock/z87_extreme3/board_info.txt A src/mainboard/asrock/z87_extreme3/bootblock.c A src/mainboard/asrock/z87_extreme3/data.vbt A src/mainboard/asrock/z87_extreme3/devicetree.cb A src/mainboard/asrock/z87_extreme3/dsdt.asl A src/mainboard/asrock/z87_extreme3/gma-mainboard.ads A src/mainboard/asrock/z87_extreme3/gpio.c A src/mainboard/asrock/z87_extreme3/hda_verb.c A src/mainboard/asrock/z87_extreme3/romstage.c 15 files changed, 530 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig b/src/mainboard/asrock/z87_extreme3/Kconfig new file mode 100644 index 0000000..0b03123 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_EXTREME3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_extreme3" + +config MAINBOARD_PART_NUMBER + default "Z87 Extreme3" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB3_0_1 (Upper) + # Header: USB2_3 +endif diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig.name b/src/mainboard/asrock/z87_extreme3/Kconfig.name new file mode 100644 index 0000000..3b90f10 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_EXTREME3 + bool "Z87 Extreme3" diff --git a/src/mainboard/asrock/z87_extreme3/Makefile.mk b/src/mainboard/asrock/z87_extreme3/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_extreme3/acpi/ec.asl b/src/mainboard/asrock/z87_extreme3/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme3/acpi/platform.asl b/src/mainboard/asrock/z87_extreme3/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_extreme3/acpi/superio.asl b/src/mainboard/asrock/z87_extreme3/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme3/board_info.txt b/src/mainboard/asrock/z87_extreme3/board_info.txt new file mode 100644 index 0000000..6e3ed58 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Extreme3/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_extreme3/bootblock.c b/src/mainboard/asrock/z87_extreme3/bootblock.c new file mode 100644 index 0000000..7a6607c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_extreme3/data.vbt b/src/mainboard/asrock/z87_extreme3/data.vbt new file mode 100644 index 0000000..d592fa6 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87_extreme3/devicetree.cb b/src/mainboard/asrock/z87_extreme3/devicetree.cb new file mode 100644 index 0000000..fe5c43b --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/devicetree.cb @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PCIE2 + end + device pci 01.1 on # PCIE3 + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off # MEI #2 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0xc892 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 on # RP #6: PCIE1 x1 slot + subsystemid 0x1849 0x8c1a + end + device pci 1c.6 on # RP #7: ASM1083/1085 PCIe to PCI Bridge + subsystemid 0x1849 0x244e + end + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x3b # + ECP and EPP 1.9 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/asrock/z87_extreme3/dsdt.asl b/src/mainboard/asrock/z87_extreme3/dsdt.asl new file mode 100644 index 0000000..17c44b6 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads b/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads new file mode 100644 index 0000000..cab2ff7 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- D-SUB + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_extreme3/gpio.c b/src/mainboard/asrock/z87_extreme3/gpio.c new file mode 100644 index 0000000..54dd668 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_extreme3/hda_verb.c b/src/mainboard/asrock/z87_extreme3/hda_verb.c new file mode 100644 index 0000000..8c07b98 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1849c892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1849c892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_extreme3/romstage.c b/src/mainboard/asrock/z87_extreme3/romstage.c new file mode 100644 index 0000000..52e7f00 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87 Pro4 (Haswell)
by Angel Pons (Code Review) 19 Jan '25

19 Jan '25

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85756?usp=email ) Change subject: mb/asrock: Add Z87 Pro4 (Haswell) ...................................................................... mb/asrock: Add Z87 Pro4 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - D-Sub Port - RJ-45 Gigabit LAN Port - All four USB 2.0 Ports - All four USB 3.1 Gen1 Ports - Vertical Type A USB 3.1 Gen1 (located next to RAM slots) - All six SATA3 6.0 Gb/s connectors - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both USB 3.1 Gen1 headers (also not working on vendor firmware, possible hardware defect) not (yet) tested: - IR header - COM Port header - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85756 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/z87_pro4/Kconfig A src/mainboard/asrock/z87_pro4/Kconfig.name A src/mainboard/asrock/z87_pro4/Makefile.mk A src/mainboard/asrock/z87_pro4/acpi/ec.asl A src/mainboard/asrock/z87_pro4/acpi/platform.asl A src/mainboard/asrock/z87_pro4/acpi/superio.asl A src/mainboard/asrock/z87_pro4/board_info.txt A src/mainboard/asrock/z87_pro4/bootblock.c A src/mainboard/asrock/z87_pro4/data.vbt A src/mainboard/asrock/z87_pro4/devicetree.cb A src/mainboard/asrock/z87_pro4/dsdt.asl A src/mainboard/asrock/z87_pro4/gma-mainboard.ads A src/mainboard/asrock/z87_pro4/gpio.c A src/mainboard/asrock/z87_pro4/hda_verb.c A src/mainboard/asrock/z87_pro4/romstage.c 15 files changed, 519 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/z87_pro4/Kconfig b/src/mainboard/asrock/z87_pro4/Kconfig new file mode 100644 index 0000000..dee318d --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_PRO4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_pro4" + +config MAINBOARD_PART_NUMBER + default "Z87 Pro4" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: LAN_USB23 (Upper) + # Header: USB_4_5 +endif diff --git a/src/mainboard/asrock/z87_pro4/Kconfig.name b/src/mainboard/asrock/z87_pro4/Kconfig.name new file mode 100644 index 0000000..61eed18 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_PRO4 + bool "Z87 Pro4" diff --git a/src/mainboard/asrock/z87_pro4/Makefile.mk b/src/mainboard/asrock/z87_pro4/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_pro4/acpi/ec.asl b/src/mainboard/asrock/z87_pro4/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_pro4/acpi/platform.asl b/src/mainboard/asrock/z87_pro4/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_pro4/acpi/superio.asl b/src/mainboard/asrock/z87_pro4/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z87_pro4/board_info.txt b/src/mainboard/asrock/z87_pro4/board_info.txt new file mode 100644 index 0000000..ab362f2 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Pro4/ +ROM protocol: SPI +Flashrom support: n +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_pro4/bootblock.c b/src/mainboard/asrock/z87_pro4/bootblock.c new file mode 100644 index 0000000..f38cf78 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x60); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_pro4/data.vbt b/src/mainboard/asrock/z87_pro4/data.vbt new file mode 100644 index 0000000..839134b --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87_pro4/devicetree.cb b/src/mainboard/asrock/z87_pro4/devicetree.cb new file mode 100644 index 0000000..330e8f7 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/devicetree.cb @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0251" + register "gpe0_en_1" = "0x246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI 1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI 2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x8892 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3: ASM1083/1085 PCIe to PCI Bridge + subsystemid 0x1849 0x244e + end + device pci 1c.3 off end # RP #4 + device pci 1c.4 on # RP #5: PCIE3 + subsystemid 0x1849 0x8c18 + end + device pci 1c.5 off end # RP #6 + device pci 1c.6 on # RP #7: PCIE2 + subsystemid 0x1849 0x8c1c + end + device pci 1c.7 on # RP #8: PCIE4 + subsystemid 0x1849 0x8c1e + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87_pro4/dsdt.asl b/src/mainboard/asrock/z87_pro4/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87_pro4/gma-mainboard.ads b/src/mainboard/asrock/z87_pro4/gma-mainboard.ads new file mode 100644 index 0000000..8db057d --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- D-Sub + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_pro4/gpio.c b/src/mainboard/asrock/z87_pro4/gpio.c new file mode 100644 index 0000000..7423c78 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/gpio.c @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_pro4/hda_verb.c b/src/mainboard/asrock/z87_pro4/hda_verb.c new file mode 100644 index 0000000..038ad1f --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4025e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_pro4/romstage.c b/src/mainboard/asrock/z87_pro4/romstage.c new file mode 100644 index 0000000..9ad77c7 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/romstage.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Gerrit-Change-Number: 85756 Gerrit-PatchSet: 7 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: [only for test] test build llvm 18.1.7
by Elyes Haouas (Code Review) 19 Jan '25

19 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86054?usp=email ) Change subject: [only for test] test build llvm 18.1.7 ...................................................................... [only for test] test build llvm 18.1.7 Change-Id: I0edf2d65552a6882a0bc48f3bd643c077a877b3d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc A util/crossgcc/sum/clang-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.7.src.tar.xz.cksum D util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum 15 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/86054/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a751003..d23fba2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -43,7 +43,7 @@ BINUTILS_VERSION=2.43.1 IASL_VERSION=20241212 # CLANG version number -CLANG_VERSION=18.1.8 +CLANG_VERSION=18.1.7 CMAKE_VERSION=3.31.3 NASM_VERSION=2.16.03 diff --git a/util/crossgcc/sum/clang-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/clang-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..85919a6 --- /dev/null +++ b/util/crossgcc/sum/clang-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +2d732f398c9f419e9b3f7925f0c7a7c52184128a tarballs/clang-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum deleted file mode 100644 index a517ab9..0000000 --- a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -581e929ba0d9fafc555081ab18d8c3fdf4478ac2 tarballs/clang-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..f718203 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +efd262a6cad00ac709d49477f5c4f573e6b69294 tarballs/clang-tools-extra-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 6b9b67c..0000000 --- a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -32923b812700526b76451384e4662ca45360d564 tarballs/clang-tools-extra-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/cmake-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/cmake-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..3e9deda --- /dev/null +++ b/util/crossgcc/sum/cmake-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +a0fe6778a79bf0ac51be069a7cd8e6d2599b68f9 tarballs/cmake-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum deleted file mode 100644 index d0e6331..0000000 --- a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -1ea03e355b705b4cada3051bd7301a57daa19283 tarballs/cmake-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..57948d0 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +7b0866e908342ccfd4403ecefd3d466ddcc05341 tarballs/compiler-rt-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 711ef35..0000000 --- a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6ecbfa5516b60adb4e4e60f991b0d8ddf5aab12a tarballs/compiler-rt-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/libunwind-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..9045dee --- /dev/null +++ b/util/crossgcc/sum/libunwind-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +925d0452a35f5d461d4cdc2d0fab4bcf1afb27ec tarballs/libunwind-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum deleted file mode 100644 index d3819e3..0000000 --- a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5bee6cd2847f6d468861c78a21236e1c6fdc8374 tarballs/libunwind-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/lld-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/lld-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..d378b82 --- /dev/null +++ b/util/crossgcc/sum/lld-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +3b024f9b5d6307b72651e8a759ba8c84f28ee2c3 tarballs/lld-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 490a835..0000000 --- a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -1cf1fa9848b05a07d3d52e69949d44003f2ab2af tarballs/lld-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/llvm-18.1.7.src.tar.xz.cksum b/util/crossgcc/sum/llvm-18.1.7.src.tar.xz.cksum new file mode 100644 index 0000000..9d90788 --- /dev/null +++ b/util/crossgcc/sum/llvm-18.1.7.src.tar.xz.cksum @@ -0,0 +1 @@ +824957de63cb2edf525a0e6f1fa290ea0e2791bd tarballs/llvm-18.1.7.src.tar.xz diff --git a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 4845fb5..0000000 --- a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f9befa4cbef3f688ab48fca42449e13c5bcb872d tarballs/llvm-18.1.8.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/86054?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0edf2d65552a6882a0bc48f3bd643c077a877b3d Gerrit-Change-Number: 86054 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: AArch64: Drop unused and deprecated ILP32
by Elyes Haouas (Code Review) 19 Jan '25

19 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86053?usp=email ) Change subject: AArch64: Drop unused and deprecated ILP32 ...................................................................... AArch64: Drop unused and deprecated ILP32 GCC-15 deprecates (-mabi=ilp32), so remove unused RV32. Change-Id: Ie1cb249541d9afd893df6dde0111ad45c8a5ff98 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 M payloads/external/Makefile.mk M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk M src/arch/riscv/fit_payload.c M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/pmp.c M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig.name M src/soc/ucb/riscv/Kconfig D util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch M util/qemu/Makefile.mk 14 files changed, 10 insertions(+), 174 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/86053/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index f8a718f..7dc8299 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -33,16 +33,8 @@ help AARCH64 kernel and initramfs -config LINUXBOOT_RISCV_RV32 - bool "RISC-V" - depends on ARCH_RISCV_RV32 - select PAYLOAD_FIT_SUPPORT - help - RISC-V kernel and initramfs - config LINUXBOOT_RISCV_RV64 bool "RISC-V" - depends on ARCH_RISCV_RV64 select PAYLOAD_FIT_SUPPORT help RISC-V kernel and initramfs @@ -96,7 +88,6 @@ default "i386/defconfig" if LINUXBOOT_X86 default "x86_64/defconfig" if LINUXBOOT_X86_64 default "arm64/defconfig" if LINUXBOOT_ARM64 - default "riscv/defconfig-32" if LINUXBOOT_RISCV_RV32 default "riscv/defconfig-64" if LINUXBOOT_RISCV_RV64 help Path to the kernel configuration file. @@ -106,7 +97,7 @@ choice prompt "Kernel binary format" default LINUXBOOT_KERNEL_BZIMAGE if LINUXBOOT_X86 || LINUXBOOT_X86_64 - default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64 + default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV64 config LINUXBOOT_KERNEL_BZIMAGE bool "bzImage" @@ -114,13 +105,13 @@ config LINUXBOOT_KERNEL_UIMAGE bool "uImage" - depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64 + depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV64 endchoice config LINUXBOOT_DTS_FILE string "Compiled devicetree file" - depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64 + depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV64 default "empty.dts" endif #LINUXBOOT_COMPILE_KERNEL @@ -152,7 +143,6 @@ config LINUXBOOT_UROOT bool "u-root" - depends on !LINUXBOOT_RISCV_RV32 # not supported by u-root help Enable u-root linuxboot mode. See http://u-root.tk/ for more information. diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 83b8d6e..c9d805a 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -7,7 +7,6 @@ LINUX_ARCH-$(CONFIG_LINUXBOOT_X86_64) = x86_64 LINUX_ARCH-$(CONFIG_LINUXBOOT_X86) = i386 LINUX_ARCH-$(CONFIG_LINUXBOOT_ARM64) = arm64 -LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y) diff --git a/payloads/external/LinuxBoot/riscv/defconfig-32 b/payloads/external/LinuxBoot/riscv/defconfig-32 deleted file mode 100644 index f6af0f7..0000000 --- a/payloads/external/LinuxBoot/riscv/defconfig-32 +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_ARCH_RV32I=y -CONFIG_32BIT=y -# CONFIG_PORTABLE is not set -CONFIG_NONPORTABLE=y diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 299f1ee..d0c907d 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -388,7 +388,6 @@ LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86_64) = x86_64 LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_ARM) = arm LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_ARM64) = arm64 -LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),y) ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH),"") @@ -406,7 +405,6 @@ CONFIG_LINUXBOOT_X86=$(CONFIG_LINUXBOOT_X86) \ CONFIG_LINUXBOOT_ARM=$(CONFIG_LINUXBOOT_ARM) \ CONFIG_LINUXBOOT_ARM64=$(CONFIG_LINUXBOOT_ARM64) \ - CONFIG_LINUXBOOT_RISCV_RV32=$(CONFIG_LINUXBOOT_RISCV_RV32) \ CONFIG_LINUXBOOT_RISCV_RV64=$(CONFIG_LINUXBOOT_RISCV_RV64) \ CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH) \ CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \ diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index b7fc0ca..2aaa805 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -4,10 +4,6 @@ bool select ARCH_RISCV -config ARCH_RISCV_RV32 - bool - select ARCH_RISCV - config ARCH_RISCV bool diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index bda392a..3526359 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -11,15 +11,7 @@ riscv_flags = -I$(src)/arch/riscv/ -ifeq ($(CONFIG_ARCH_RISCV_RV64),y) _rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 -else -ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -_rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32 -else -$(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32") -endif -endif # Needed for -print-libgcc-file-name which gets confused about all those arch # suffixes in ARCH_SUFFIX_riscv. @@ -80,10 +72,6 @@ bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags) -ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -LDFLAGS_bootblock += -m elf32lriscv -endif #CONFIG_ARCH_RISCV_RV32 - endif #CONFIG_ARCH_BOOTBLOCK_RISCV ################################################################################ @@ -100,10 +88,6 @@ romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) -ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -LDFLAGS_romstage += -m elf32lriscv -endif #CONFIG_ARCH_RISCV_RV32 - endif #CONFIG_ARCH_ROMSTAGE_RISCV ################################################################################ @@ -128,10 +112,6 @@ ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) -ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -LDFLAGS_ramstage += -m elf32lriscv -endif #CONFIG_ARCH_RISCV_RV32 - endif #CONFIG_ARCH_RAMSTAGE_RISCV ifeq ($(CONFIG_RISCV_OPENSBI),y) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index bfa0c98..5ebf473 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -10,13 +10,7 @@ /* Implements a Berkeley Boot Loader (BBL) compatible payload loading */ #define MAX_KERNEL_SIZE (64*MiB) - -#if CONFIG(ARCH_RISCV_RV32) -#define SECTION_ALIGN (4 * MiB) -#endif -#if CONFIG(ARCH_RISCV_RV64) #define SECTION_ALIGN (2 * MiB) -#endif static size_t get_kernel_size(const struct fit_image_node *node) { diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h index 273ccfe..8d02f69 100644 --- a/src/arch/riscv/include/arch/pmp.h +++ b/src/arch/riscv/include/arch/pmp.h @@ -16,10 +16,7 @@ /* reset PMP setting */ void reset_pmp(void); -/* - * set up PMP record - * reminder: base and size are 34-bits on RV32. - */ +/* set up PMP record */ void setup_pmp(u64 base, u64 size, u8 flags); /* write the last PMP record, i.e. the "default" case. */ diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index cb605cb..d8b11a3 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -252,22 +252,11 @@ p->address = (base + size); } -/* - * Generate a PMP configuration. - * reminder: base and size are 34 bit numbers on RV32. - */ +/* Generate a PMP configuration */ static int generate_pmp(struct pmpcfg *p, u64 base, u64 size, u8 flags) { - /* Convert the byte address and byte size to units of 32-bit words */ uintptr_t b = (uintptr_t) base >> PMP_SHIFT, s = (uintptr_t) size >> PMP_SHIFT; -#if __riscv_xlen == 32 - /* verify that base + size fits in 34 bits */ - if ((base + size - 1) >> 34) { - printk(BIOS_EMERG, "%s: base (%llx) + size (%llx) - 1 is more than 34 bits\n", - __func__, base, size); - return 1; - } -#endif + /* if base is -1, that means "match all" */ if (base == (u64)-1) { generate_pmp_all(p); @@ -371,19 +360,7 @@ } } -/* - * set up PMP record - * Why are these u64 and not uintptr_t? - * because, per the spec: - * The Sv32 page-based virtual-memory scheme described in Section 4.3 - * supports 34-bit physical addresses for RV32, so the PMP scheme must - * support addresses wider than XLEN for RV32. - * Yes, in RV32, these are 34-bit numbers. - * Rather than require every future user of these to remember that, - * this ABI is 64 bits. - * generate_pmp will check for out of range values. - */ -void setup_pmp(u64 base, u64 size, u8 flags) +void setup_pmp(uintptr_t base, u64 size, u8 flags) { struct pmpcfg p; int is_range, n; diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 9b5a6f0..2f6e356 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -11,13 +11,6 @@ select ARCH_RISCV_RV64 endif -if BOARD_EMULATION_QEMU_RISCV_RV32 - -config BOARD_EMULATION_QEMU_RISCV - def_bool y - select ARCH_RISCV_RV32 -endif - if BOARD_EMULATION_QEMU_RISCV config BOARD_SPECIFIC_OPTIONS @@ -52,18 +45,15 @@ config RISCV_ARCH string - default "rv64imafd" if ARCH_RISCV_RV64 - default "rv32im" if ARCH_RISCV_RV32 + default "rv64imafd" config RISCV_ABI string - default "lp64d" if ARCH_RISCV_RV64 - default "ilp32" if ARCH_RISCV_RV32 + default "lp64d" config RISCV_CODEMODEL string - default "medany" if ARCH_RISCV_RV64 - default "medany" if ARCH_RISCV_RV32 + default "medany" config RISCV_WORKING_HARTID int diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig.name b/src/mainboard/emulation/qemu-riscv/Kconfig.name index 3bbc6c5..bfc678a 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig.name +++ b/src/mainboard/emulation/qemu-riscv/Kconfig.name @@ -2,6 +2,3 @@ config BOARD_EMULATION_QEMU_RISCV_RV64 bool "QEMU RISC-V rv64" - -config BOARD_EMULATION_QEMU_RISCV_RV32 - bool "QEMU RISC-V rv32" diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index bd0945e..ec1d610 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -14,8 +14,6 @@ if SOC_UCB_RISCV -if ARCH_RISCV_RV64 - config RISCV_ARCH string default "rv64imafd" @@ -28,24 +26,6 @@ string default "medany" -endif - -if ARCH_RISCV_RV32 - -config RISCV_ARCH - string - default "rv32im" - -config RISCV_ABI - string - default "ilp32" - -config RISCV_CODEMODEL - string - default "medany" - -endif - config RISCV_WORKING_HARTID int default 0 diff --git a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch deleted file mode 100644 index 5b0d715..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 88bc675eab98cea388daf40396686178ca5fcdb3 Mon Sep 17 00:00:00 2001 -From: Peter Marheine <pmarheine(a)chromium.org> -Date: Mon, 15 Aug 2022 11:01:50 +1000 -Subject: [PATCH] riscv: elf-multilib: add rv32iafc to defaults - -rv32iafc-ilp32 is compatible with rv32iac-ilp32 for library -implementation, so add a reuse rule allowing the default configuration -to support rv32iafc. - --IAFC is an unusual configuration (much less common than -IMAFC), but -multilib reuse has essentially no cost: this change is useful to users -of platforms that support hardware floating-point but cannot use -hardware multiply/divide for any reason. To avoid generating a new set -of libraries this is limited to the soft-float ABI. - -Tested by verifying that `gcc -march=rv32iafc -mabi=ilp32 ---print-search-dirs` refers to the rv32iac/ilp32 library directory as -expected, rather than just the root library directory as occurs when an -unsupported target is selected (for instance, rv32id). - -Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> ---- - gcc/config/riscv/t-elf-multilib | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/riscv/t-elf-multilib b/gcc/config/riscv/t-elf-multilib -index 19f9434616c..6e74b1811be 100644 ---- a/gcc/config/riscv/t-elf-multilib -+++ b/gcc/config/riscv/t-elf-multilib -@@ -1,11 +1,12 @@ - # This file was generated by multilib-generator with the command: --# ./multilib-generator rv32i-ilp32--c rv32im-ilp32--c rv32iac-ilp32-- rv32imac-ilp32-- rv32imafc-ilp32f-rv32imafdc- rv64imac-lp64-- rv64imafdc-lp64d-- --MULTILIB_OPTIONS = march=rv32i/march=rv32ic/march=rv32im/march=rv32imc/march=rv32iac/march=rv32imac/march=rv32imafc/march=rv32imafdc/march=rv32gc/march=rv64imac/march=rv64imafdc/march=rv64gc mabi=ilp32/mabi=ilp32f/mabi=lp64/mabi=lp64d -+# ./multilib-generator rv32i-ilp32--c rv32im-ilp32--c rv32iac-ilp32--f rv32imac-ilp32-- rv32imafc-ilp32f-rv32imafdc- rv64imac-lp64-- rv64imafdc-lp64d-- -+MULTILIB_OPTIONS = march=rv32i/march=rv32ic/march=rv32im/march=rv32imc/march=rv32iac/march=rv32iafc/march=rv32imac/march=rv32imafc/march=rv32imafdc/march=rv32gc/march=rv64imac/march=rv64imafdc/march=rv64gc mabi=ilp32/mabi=ilp32f/mabi=lp64/mabi=lp64d - MULTILIB_DIRNAMES = rv32i \ - rv32ic \ - rv32im \ - rv32imc \ - rv32iac \ -+rv32iafc \ - rv32imac \ - rv32imafc \ - rv32imafdc \ -@@ -25,6 +26,7 @@ march=rv64imac/mabi=lp64 \ - march=rv64imafdc/mabi=lp64d - MULTILIB_REUSE = march.rv32i/mabi.ilp32=march.rv32ic/mabi.ilp32 \ - march.rv32im/mabi.ilp32=march.rv32imc/mabi.ilp32 \ -+march.rv32iac/mabi.ilp32=march.rv32iafc/mabi.ilp32 \ - march.rv32imafc/mabi.ilp32f=march.rv32imafdc/mabi.ilp32f \ - march.rv32imafc/mabi.ilp32f=march.rv32gc/mabi.ilp32f \ - march.rv64imafdc/mabi.lp64d=march.rv64gc/mabi.lp64d --- -2.37.1.595.g718a3a8f04-goog - diff --git a/util/qemu/Makefile.mk b/util/qemu/Makefile.mk index 7b9b636..865184f 100644 --- a/util/qemu/Makefile.mk +++ b/util/qemu/Makefile.mk @@ -32,9 +32,6 @@ QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64) ?= qemu-system-riscv64 -M virt -m 1G -drive \ if=pflash,file=build/coreboot.rom,format=raw -QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV32) ?= qemu-system-riscv32 -M virt -m 1G -drive \ - if=pflash,file=build/coreboot.rom,format=raw - QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_I440FX) ?= qemu-system-x86_64 -M pc QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= qemu-system-x86_64 -M q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/86053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1cb249541d9afd893df6dde0111ad45c8a5ff98 Gerrit-Change-Number: 86053 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86035?usp=email ) Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... soc/mediatek/common: Fix wrong write API for protect_key_setting When writing key_protect_setting to PMIC, PMIC expects receiving 1 byte per write. PMIC would receive unexpected zero byte if using mt6685_write16. Fix the write operation by using mt6685_write8. TEST=Build pass. BUG=b:388666377 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86035 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/mt6685.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/mt6685.c b/src/soc/mediatek/common/mt6685.c index 7d17556..0d43c7b 100644 --- a/src/soc/mediatek/common/mt6685.c +++ b/src/soc/mediatek/common/mt6685.c @@ -74,8 +74,8 @@ static void mt6685_unlock(bool unlock) { for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) - mt6685_write16(key_protect_setting[i].addr, - unlock ? key_protect_setting[i].val : 0); + mt6685_write8(key_protect_setting[i].addr, + unlock ? key_protect_setting[i].val : 0); } void mt6685_init_pmif_arb(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025