coreboot-gerrit January 2025

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Keith Hui. Hello Bill XIE, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85413?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... mb/asus/p8z77-v: Attempt to correctly route PCIe lanes Bill Xie documented in his initial code drop that he was unsuccessful in reproducing all the PCIe configurations possible with vendor firmware. I obtained a boardview to this board and have identified the PCIe lane topology and the required control signals. There are PCIe slot presence signals wired to GPIOs 34,20,7 for PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D super I/O chip. PCIe lanes 5-8 are fixed. With these details, it is now possible to attempt to reproduce all the vendor PCIe configurations. 1. Change GPIO20 of PCH to GPIO input so coreboot can detect a card inserted into PCIEX1_2. 2. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its two SATA 6Gbps ports. Another one needs to be added later to enable users to allocate all lanes to PCIEX16_3 and make it x4. 3. Add code to bootblock to check the PCHSTRP9 soft strap and whether (1) is true. There is a sanity check to warn of a PCIe configuration that is not valid on this board. 4. Based on (1) and (2), program SIO GPIO5 as appropriate. Remove all GPIO5 settings from devicetree so this code has full control. Changing PCIEX16_3 from x1 to x4 (and vice versa) requires changing PCHSTRP9 in the SPI flash descriptor. How coreboot can manage this is TBD. This is based on boardview only, and is untested because I have no hardware. Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb 5 files changed, 113 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add unmask eint event for bootblock
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Chhao Chang, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: Add unmask eint event for bootblock ...................................................................... Patch Set 18: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84025/comment/5b73fdcb_90685334?us… : PS17, Line 12: ' > " Done https://review.coreboot.org/c/coreboot/+/84025/comment/f64348f5_c82399a7?us… : PS17, Line 12: ' > " Done https://review.coreboot.org/c/coreboot/+/84025/comment/ca645536_234b57db?us… : PS17, Line 16: 31709620 > Wrong bug? Done File src/soc/mediatek/common/eint_event.c: https://review.coreboot.org/c/coreboot/+/84025/comment/ec3a1e26_ebc27e8a?us… : PS17, Line 15: uintptr_t reg; > My approach do the same way. Done https://review.coreboot.org/c/coreboot/+/84025/comment/7a246179_bc373b53?us… : PS17, Line 8: #define EVENT_CLEAN_MASK_OFFSET 0x880 : #define EVENT_MASK_OFFSET 0x800 : #define EINT_VALUE 0xFFFFFFFF : : void enable_eint_event(uintptr_t base, unsigned int port) : { : unsigned int i; : uintptr_t reg; : : for (i = 0; i < port; i++) { : reg = base + EVENT_CLEAN_MASK_OFFSET + (i << 2); : write32((uint32_t *)reg, EINT_VALUE); : } : } > That is why there should be eint_event_common.c. Done File src/soc/mediatek/common/include/soc/eint_event.h: https://review.coreboot.org/c/coreboot/+/84025/comment/d50b10bc_5d7dbba2?us… : PS17, Line 17: struct eint_info { : uintptr_t base; : unsigned int eint_num; : }; > I uploaded CB:86033 to do the refactoring for you. Please take a look. […] Done File src/soc/mediatek/mt8196/bootblock.c: https://review.coreboot.org/c/coreboot/+/84025/comment/e8c74353_ae4fbd3c?us… : PS17, Line 9: #include <soc/eint_event.h> > sort Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 15:45:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add unmask eint event for bootblock
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Chhao Chang, Jarried Lin. Hello Chhao Chang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84025?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add unmask eint event for bootblock ...................................................................... soc/mediatek/mt8196: Add unmask eint event for bootblock EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue "Can't wake using power button (cros_ec) or touchpad". So we add a driver here to unmask all wakeup sources. TEST=write eint data successfully. BUG=b:317009620 Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Signed-off-by: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/eint_event_info.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/84025/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek: Correct value's data type to u8 in dptx
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85948?usp=email ) Change subject: soc/mediatek: Correct value's data type to u8 in dptx ...................................................................... soc/mediatek: Correct value's data type to u8 in dptx TEST=build pass BUG=b:343351631 Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85948 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h 3 files changed, 8 insertions(+), 8 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index 28a1480..91fbddf 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -79,7 +79,7 @@ } bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, - int swing_value, int preemphasis) + u8 swing_value, u8 preemphasis) { printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n", lane_num, swing_value, preemphasis); @@ -220,7 +220,7 @@ mtk_dp_write_byte(mtk_dp, 0x1038, BIT(0), BIT(0)); } -void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, int value) +void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value) { if (value == 0) mtk_dp_write_byte(mtk_dp, REG_35F0_DP_TRANS_P0, @@ -239,7 +239,7 @@ } } -void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value) +void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value) { /* Power off TPLL and lane */ mtk_dp_write(mtk_dp, 0x2000, 0x00000001); diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index fda1b4f..43fe2f5 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -498,7 +498,7 @@ GENMASK(7, 5)); } -void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value) +void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, u8 value) { /* if Set TPS1. */ if (value == BIT(4)) diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 7f0e30f..9c55318 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -63,7 +63,7 @@ bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *data); bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, - int swing_value, int preemphasis); + u8 swing_value, u8 preemphasis); u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp); u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset); void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); @@ -81,10 +81,10 @@ void dptx_hal_phy_setting(struct mtk_dp *mtk_dp); void dptx_hal_aux_setting(struct mtk_dp *mtk_dp); void dptx_hal_digital_setting(struct mtk_dp *mtk_dp); -void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, int value); +void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value); void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable); void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp); -void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value); +void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, u8 value); void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable); void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable); void dptx_hal_init_setting(struct mtk_dp *mtk_dp); @@ -100,7 +100,7 @@ void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]); void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth); void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 color_format); -void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value); +void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value); void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable); #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85948?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Gerrit-Change-Number: 85948 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek: Correct value's data type to u8 in dptx
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85948?usp=email ) Change subject: soc/mediatek: Correct value's data type to u8 in dptx ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85948?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Gerrit-Change-Number: 85948 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 15:10:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86028?usp=email ) Change subject: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow ...................................................................... soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow In the current eDP initialization flow, eDP is configured and enabled before display data pipe (DDP) initialization. The init flow is wrong, because eDP should be enabled only after DDP is correctly set up. The wrong flow may lead to garbage display between enabling eDP and configuring DDP. To fix the problem, the dptx_video_enable(true) call needs to be moved after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP enablement, to be separated from the existing mtk_edp_init(). The fixed eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable. Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86028 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/display.c M src/soc/mediatek/common/dp/dptx.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h 3 files changed, 35 insertions(+), 15 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index a212805..c7493fe 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -37,7 +37,13 @@ return NULL; } -__weak int mtk_edp_init(struct edid *edid) +__weak int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid) +{ + printk(BIOS_WARNING, "%s: Not supported\n", __func__); + return -1; +} + +__weak int mtk_edp_enable(struct mtk_dp *mtk_dp) { printk(BIOS_WARNING, "%s: Not supported\n", __func__); return -1; @@ -52,7 +58,8 @@ int mtk_display_init(void) { - struct edid edid; + struct edid edid = {0}; + struct mtk_dp mtk_edp = {0}; struct fb_info *info; const char *name; struct panel_description *panel = get_active_panel(); @@ -76,7 +83,7 @@ if (panel->disp_path == DISP_PATH_EDP) { mdelay(200); - if (mtk_edp_init(&edid) < 0) { + if (mtk_edp_init(&mtk_edp, &edid) < 0) { printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); return -1; } @@ -120,6 +127,14 @@ edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_mode_set(&edid, panel->disp_path); + + if (panel->disp_path == DISP_PATH_EDP) { + if (mtk_edp_enable(&mtk_edp) < 0) { + printk(BIOS_ERR, "%s: Failed to enable eDP\n", __func__); + return -1; + } + } + info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); if (info) fb_set_orientation(info, panel->orientation); diff --git a/src/soc/mediatek/common/dp/dptx.c b/src/soc/mediatek/common/dp/dptx.c index b0afb89..6cf590d 100644 --- a/src/soc/mediatek/common/dp/dptx.c +++ b/src/soc/mediatek/common/dp/dptx.c @@ -478,29 +478,32 @@ dptx_hal_hpd_int_en(mtk_dp, true); } -int mtk_edp_init(struct edid *edid) +int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid) { - struct mtk_dp mtk_edp; + dptx_init_variable(mtk_dp); + dptx_init_port(mtk_dp); - dptx_init_variable(&mtk_edp); - dptx_init_port(&mtk_edp); - - if (!dptx_hal_hpd_high(&mtk_edp)) { + if (!dptx_hal_hpd_high(mtk_dp)) { printk(BIOS_ERR, "HPD is low\n"); return -1; } - dptx_check_sinkcap(&mtk_edp); + dptx_check_sinkcap(mtk_dp); - if (dptx_get_edid(&mtk_edp, edid) != 0) { + if (dptx_get_edid(mtk_dp, edid) != 0) { printk(BIOS_ERR, "Failed to get EDID\n"); return -1; } - dptx_set_trainingstart(&mtk_edp); + dptx_set_trainingstart(mtk_dp); dp_intf_config(edid); - dptx_video_config(&mtk_edp); - dptx_video_enable(&mtk_edp, true); + dptx_video_config(mtk_dp); return 0; } + +int mtk_edp_enable(struct mtk_dp *mtk_dp) +{ + dptx_video_enable(mtk_dp, true); + return 0; +} diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index 1d7e135..3ed71a9 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -211,7 +211,9 @@ bool powered; }; -int mtk_edp_init(struct edid *edid); +int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid); +int mtk_edp_enable(struct mtk_dp *mtk_dp); + bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rxbuf); bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/86028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Gerrit-Change-Number: 86028 Gerrit-PatchSet: 6 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yu-Ping Wu (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/e2ec5b3d_738162fa?us… : PS4, Line 39: 0xA << 2 > `mtk_dp_mask(mtk_dp, REG_3F28_DP_ENC_4P_3, 0xA << 2, GENMAKS(5, 2));` That's even better. -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 15:02:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 6: (10 comments) File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/949eac59_41bc0a10?us… : PS6, Line 32: const struct mtk_dvo_sync_param *sync) exceed 96 characters File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/0393baea_e127edad?us… : PS6, Line 260: 0x1f 0x1F https://review.coreboot.org/c/coreboot/+/85949/comment/29fed030_df07e820?us… : PS6, Line 272: 0xbf 0xBF https://review.coreboot.org/c/coreboot/+/85949/comment/9764ad9f_e4dd9387?us… : PS6, Line 376: int mtk_edp_init(struct mtk_dp *mtk_dp,struct edid *edid) > `space required after that ',' (ctx:VxV)` Please fix. https://review.coreboot.org/c/coreboot/+/85949/comment/f809fa33_8f6cec70?us… : PS6, Line 384: mdelay are you sure this delay it correct ? File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/cc740550_82131c5b?us… : PS4, Line 39: 0xA << 2 > 0x28 `mtk_dp_mask(mtk_dp, REG_3F28_DP_ENC_4P_3, 0xA << 2, GENMAKS(5, 2));` File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/e7731b24_908d8375?us… : PS6, Line 316: mdelay why does it take a long time ? https://review.coreboot.org/c/coreboot/+/85949/comment/63eeb49f_926d7d4a?us… : PS6, Line 338: mdelay why does it take a long time ? File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/7c87787d_50ab5cee?us… : PS6, Line 137: 0x6c 0x6C https://review.coreboot.org/c/coreboot/+/85949/comment/ec87d085_f28d84ff?us… : PS6, Line 141: c C -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 14:58:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Keith Hui. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 2: (2 comments) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/8c351c64_bf676bde?us… : PS1, Line 67: gpio5 |= 0x20; > I think I have all GPIO signals figured out, and wrote what I found into early_init.c. […] PCHSTRP9 : 0x30004d80, I also have another three descriptors with PCHSTRP9 0x30004d81, 0x30004d82, 0x30004d83. My board's PCB revision is 1.02. pcie_rp4 remains wired to ASM1061 when a card is present on PCIEX1_2, inteltool says: gpiobase+0x000c: 0xe8ab7ffe (GP_LVL) and superiotool said: LDN 0x09 idx 30 ... f4 f5 ... val ff ... 8f c8 ... def 00 ... ff 00 ... If no card is present on PCIEX1_2, GP_LVL is 0xe8bb7ffe and LDN 0x09 is idx 30 ... f4 f5 ... val ff ... 8f c8 ... def 00 ... ff 00 ... File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/c7f50048_5a08efd1?us… : PS2, Line 77: {7, 34, 20, -1} This order should be reversed to {20, 34, 7, -1}, as get_gpios() works in little-endian way. When fixed, pcie_rp4 is wired to ASM1061 without card on PCIEX1_2: LDN 0x09 idx 30 ... f4 f5 ... val ff ... 8f c8 ... def 00 ... ff 00 ... but to nothing with card on PCIEX1_2: LDN 0x09 idx 30 ... f4 f5 ... val ff ... 8f a8 ... def 00 ... ff 00 ... -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 14:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Paul Menzel (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Shunxi Zhang, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/145cbd42_89b359f3?us… : PS1, Line 167: printk(BIOS_INFO, "EOSC cali val = %#x\n", val); > Yes, it is debug msg Then use log level debug? -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 14:32:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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