coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Paul Menzel (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 8: Code-Review+1 (17 comments) Patchset: PS8: Looks good overall. It’d be great if the log messages could be improved, and also some variable types be changed to use non-fixed length types where possible. Commit Message: https://review.coreboot.org/c/coreboot/+/86017/comment/63cefa58_a7fa6d67?us… : PS8, Line 9: Add thermal driver to support LVTS (Low Voltage Thermal Sensor). This seems new for MT8196. The other SOC do not have such a driver. Could you please add some more background what changed? https://review.coreboot.org/c/coreboot/+/86017/comment/58e00223_ba08c7c6?us… : PS8, Line 10: Why is a separate SRAM driver needed? https://review.coreboot.org/c/coreboot/+/86017/comment/618f79e4_418b5fa1?us… : PS8, Line 11: TEST=Check temperatures read from each sensors. Please paste the new log messages. https://review.coreboot.org/c/coreboot/+/86017/comment/f072efcd_6e9cd9cf?us… : PS8, Line 11: TEST=Check temperatures read from each sensors. With the command `sensors`? File src/soc/mediatek/mt8196/include/soc/thermal_internal.h: https://review.coreboot.org/c/coreboot/+/86017/comment/fdb51304_5a50f55c?us… : PS8, Line 15: /* Add a blank line above? https://review.coreboot.org/c/coreboot/+/86017/comment/c82854bc_d9720d02?us… : PS8, Line 16: * module LVTS Plan Move *LVTS Plan* more to the right? File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86017/comment/fa136c70_f2e54360?us… : PS8, Line 38: */ To avoid duplication, the comment should just be in one file? https://review.coreboot.org/c/coreboot/+/86017/comment/7cd5ba3c_4c5bc135?us… : PS8, Line 163: printk(BIOS_INFO, "%s: msr_raw=%u, temp_mc=%d\n", __func__, msr_raw, temp_mc); Should be a debug message, or rewritten? https://review.coreboot.org/c/coreboot/+/86017/comment/31214c9a_3343f33f?us… : PS8, Line 170: uint32_t i; size_t? https://review.coreboot.org/c/coreboot/+/86017/comment/f3ddb0d3_1786d9cc?us… : PS8, Line 234: int i; size_t https://review.coreboot.org/c/coreboot/+/86017/comment/c0e175bd_5f23357a?us… : PS8, Line 268: int i; size_t https://review.coreboot.org/c/coreboot/+/86017/comment/2e97dde9_3478b79b?us… : PS8, Line 271: printk(BIOS_INFO, "%s\n", __func__); Looks like a debug message. https://review.coreboot.org/c/coreboot/+/86017/comment/6def15ad_a7dc4f69?us… : PS8, Line 375: * to wait HW init done, to wait *until* HW init *is* done, https://review.coreboot.org/c/coreboot/+/86017/comment/f1a3f67a_20a695ec?us… : PS8, Line 376: translates translate https://review.coreboot.org/c/coreboot/+/86017/comment/09854128_b894e73a?us… : PS8, Line 379: finish finishes https://review.coreboot.org/c/coreboot/+/86017/comment/bccf043f_318b9406?us… : PS8, Line 373: * 26111 is magic num : * this is to keep system alive for a while : * to wait HW init done, : * because 0 msr raw will translates to 28x'C : * and then 28x'C will trigger a SW reset. : * : * if HW init finish, this msr raw will not be 0, : * system can report normal temperature. : * if wait over 60 times zero, this means something : * wrong with HW, must trigger BUG on and dump useful : * register for debug. Re-flow the text? -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:40:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Paul Menzel (Code Review) 18 Jan '25

18 Jan '25

Paul Menzel has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > @paul my driver is open source https://github.com/coolstar/cbtable […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/rauru: Add thermal init flow in romstage
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Zhaoqing Jiu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86018?usp=email ) Change subject: mb/google/rauru: Add thermal init flow in romstage ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I518ffd92684a222f25d642a51e73a0faa453a8b1 Gerrit-Change-Number: 86018 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:30:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Yidi Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86035?usp=email ) Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:29:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 8: (1 comment) File src/drivers/intel/fsp2_0/debug.c: https://review.coreboot.org/c/coreboot/+/86001/comment/71c413d9_1bffdcdf?us… : PS6, Line 185: if (!CONFIG(USE_CBFS_FILE_OPTION_BACKEND)) > > Why? Why shouldn't this just work for all option backends equally? > > > > To be clear, I think this function should just be: > > ``` > > enum fsp_log_level fsp_get_pcd_debug_log_level(void) > > { > > return get_uint_option("fsp_pcd_debug_level", fsp_map_console_log_level()); > > } > > ``` > > > > [Sorry, looks like I forgot to publish this comment yesterday.] > > > Looks like you missed to read my comments previously (?) as I have mentioned why we can't call fsp_map_console_log_level as fallback because we are now stitching debug fsp by default with ap fw that means when we are not injecting options to control debug level (like default ap fw won't have any option included), we shouldn't see any debug log from fsp. Calling fsp_map_console_log_level api as fallback would mean that we are getting chatty console by default which is not intention of this CL. > > One should see more chatty console when they inject options into cbfs. If they don't select cbfs backend kconfig then this CL doesn't change the behavior of console level. I have tried to accommodate your feedback by adding another Kconfig (FSP_DYNAMIC_DEBUG) an option to control the debug log level of FSP blobs. This will allow existing Intel devices that are not intended to enable dynamic FSP debugging to continue to function correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:16:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Julius Werner, Jérémy Compostella, Nicholas Chin. Subrata Banik has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 15: (1 comment) Patchset: PS4: > Hmm... […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 15 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:12:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Jérémy Compostella, Nicholas Chin, Subrata Banik. Subrata Banik has uploaded a new patch set (#15) to the change originally created by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in CBFS with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -n option/<option-name> -i <value>`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. This backend is not available in SMM due to CBFS dependencies on vboot functions which are not added to SMM, and thus the fallback will be returned by calls to get_uint_option() in SMM. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85905/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 15 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar. Hello Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86001?usp=email to look at the new patch set (#8). Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... drivers/intel/fsp2_0: Add option to control debug log level using CBFS This commit relies on newly added Kconfig option, FSP_DYNAMIC_DEBUG, which allows controlling the FSP debug log level using CBFS options (RAW binary files). Platform that selects this option should also stitch FSP debug binary then following files will be used to control the console log levels of Intel FSP: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. In absense of these files, the FSP console log-level is considered as disabled (aka `FSP_LOG_LEVEL_DISABLE`) The values in these files should correspond to the FSP_LOG_LEVEL_* enum values. See the Kconfig help text for more details. If this option is disabled, the log levels will be determined by calling into fsp_map_console_log_level API. This change allows for more flexibility in controlling the FSP debug log level, especially in cases of debugging silicon firmware issues with a debug AP FW binary. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO CBFS, both the silicon firmware and MRC behave as debug binaries. To verify the presence of both log-level RAW CBFS binaries in the CBFS RO slot, run: ``` sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_ ``` This should output: ``` option/fsp_mrc_debug_level 0x88e40 raw 8 none option/fsp_pcd_debug_level 0x2a7400 raw 8 none ``` Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86001/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86035?usp=email ) Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/common/mt6685.c: https://review.coreboot.org/c/coreboot/+/86035/comment/51ada0f4_df5d0a01?us… : PS2, Line 78: > remove one space Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 11:03:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86035?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... soc/mediatek/common: Fix wrong write API for protect_key_setting When writing key_protect_setting to PMIC, PMIC expects receiving 1 byte per write. PMIC would receive unexpected zero byte if using mt6685_write16. Fix the write operation by using mt6685_write8. TEST=Build pass. BUG=b:388666377 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 --- M src/soc/mediatek/common/mt6685.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86035/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit January 2025