coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/mediatek/common: Fix wrong write API for protect_key_setting
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86035?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/common: Fix wrong write API for protect_key_setting ...................................................................... soc/mediatek/common: Fix wrong write API for protect_key_setting When writing key_protect_setting to PMIC, PMIC expects receiving 1 byte per write. PMIC would receive unexpected zero byte if using mt6685_write16. Fix the write operation by using mt6685_write8. TEST=Build pass. BUG=b:388666377 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 --- M src/soc/mediatek/common/mt6685.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86035/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by 9elements QA (Code Review) 18 Jan '25

18 Jan '25

9elements QA has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 21: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230239 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230237 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/230236 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/230235 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/230234 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230233 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/230232 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/230231 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230230 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/230229 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/230228 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/230227 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 21 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 10:07:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8196/thermal_sram.c: https://review.coreboot.org/c/coreboot/+/86017/comment/5e3fe49c_62517b6a?us… : PS5, Line 46: uint32_t pattern = 0xffffffff; > Upper case Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 09:50:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86017?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... soc/mediatek/mt8196: Add thermal driver Add thermal driver to support LVTS (Low Voltage Thermal Sensor). TEST=Check temperatures read from each sensors. BUG=b:317009620 Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/thermal.h A src/soc/mediatek/mt8196/include/soc/thermal_internal.h A src/soc/mediatek/mt8196/thermal.c A src/soc/mediatek/mt8196/thermal_sram.c 7 files changed, 1,033 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86017/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: CFR: Add min/max/step values and hex display flag for number options
by Angel Pons (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Filip Brozovic, Matt DeVillier, Sean Rhodes. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86039?usp=email ) Change subject: CFR: Add min/max/step values and hex display flag for number options ...................................................................... Patch Set 2: (1 comment) File src/commonlib/include/commonlib/cfr.h: https://review.coreboot.org/c/coreboot/+/86039/comment/0a8e9bc9_3837b282?us… : PS2, Line 139: uint32_t min; : uint32_t max; : uint32_t step; > Would it make more sense to instead put these values (as well as the display flags) into tagged varb […] Yes, the CFR header is where a version number would be. If there isn't one, I would suggest making that breaking change first. -- To view, visit https://review.coreboot.org/c/coreboot/+/86039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Gerrit-Change-Number: 86039 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 09:49:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Filip Brozovic <fbrozovic(a)gmail.com>

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[S] Change in coreboot[main]: CFR: Add min/max/step values and hex display flag for number options
by Angel Pons (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Filip Brozovic, Matt DeVillier, Sean Rhodes. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86039?usp=email ) Change subject: CFR: Add min/max/step values and hex display flag for number options ...................................................................... Patch Set 2: (1 comment) File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/86039/comment/4f37bce7_ba9406b9?us… : PS2, Line 123: step > At least in HII, a step size of 0 means the variable can't be changed with -/+ keys, which makes the […] Ah, wasn't aware of that. I think it makes sense, yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/86039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Gerrit-Change-Number: 86039 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 09:48:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Filip Brozovic <fbrozovic(a)gmail.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jason-jh Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Jason-jh Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86027/comment/5817429f_9e4db2d3?us… : PS4, Line 13: ang when accessing DRAM. > exceed 72 characters Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 07:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jason-jh Lin (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Jason-jh Lin. Jason-jh Lin has uploaded a new patch set (#5) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... soc/mediatek/mt8196: Add GCE ddren sel control to mminfra MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction ACK from SPM: 0, non-SPM: 0x1. In MT8196, SPM has masked all the DDR requests, so this setting should be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will hang when accessing DRAM. BUG=b:379039600 TEST=boot up ok, GCE can access DRAM continuously Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Signed-off-by: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/mminfra.h M src/soc/mediatek/mt8196/mminfra.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: CFR: Add min/max/step values and hex display flag for number options
by Filip Brozovic (Code Review) 18 Jan '25

18 Jan '25

Attention is currently required from: Angel Pons, Matt DeVillier, Sean Rhodes. Filip Brozovic has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86039?usp=email ) Change subject: CFR: Add min/max/step values and hex display flag for number options ...................................................................... Patch Set 2: (5 comments) File src/commonlib/include/commonlib/cfr.h: https://review.coreboot.org/c/coreboot/+/86039/comment/b5688568_1920de4f?us… : PS2, Line 94: * CFR_OPTFLAG_NUMBER_HEX: : * Displays a numeric option in hexadecimal instead of decimal notation. : * This flag is only valid for numeric options. > Flags are meant to be applicable to all option types. This one is not. […] Acknowledged https://review.coreboot.org/c/coreboot/+/86039/comment/365ad7c7_893573d8?us… : PS2, Line 139: uint32_t min; : uint32_t max; : uint32_t step; > This changes the structure layout in a non-backwards compatible way. […] Would it make more sense to instead put these values (as well as the display flags) into tagged varbinary structs? As far as I can see, any way we try to add a version number, we need to change _some_ struct, making it non-backwards compatible. If we do add a version number, it probably makes the most sense to add it in the `lb_cfr_header` struct? Since `min` and `max` are both `uint32_t`, it makes the most sense to make them inclusive, otherwise we have no way to set `0` and `UINT32_MAX` File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/86039/comment/08851c8d_519f6da5?us… : PS2, Line 121: option->min = min; > We should probably check that `min <= max` (both inclusive). Acknowledged https://review.coreboot.org/c/coreboot/+/86039/comment/dab0c1b8_f1fbbf17?us… : PS2, Line 122: 0xffffffff > UINT32_MAX Acknowledged https://review.coreboot.org/c/coreboot/+/86039/comment/5af3bee7_0393dd9d?us… : PS2, Line 123: step > Let's assume a step size of 0 is equivalent to 1 At least in HII, a step size of 0 means the variable can't be changed with -/+ keys, which makes the behavior different from defining it as 1. Is this behavior something we want to keep? -- To view, visit https://review.coreboot.org/c/coreboot/+/86039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Gerrit-Change-Number: 86039 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 07:18:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: mb/*: Remove old USB configs from SNB/bd82x6x boards, part 2
by Elyes Haouas (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Elyes Haouas has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85942?usp=email ) Change subject: mb/*: Remove old USB configs from SNB/bd82x6x boards, part 2 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85942?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79 Gerrit-Change-Number: 85942 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 05:58:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025