coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 00:19:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Run mtk-fsp in romstage
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86015?usp=email ) Change subject: mb/google/rauru: Run mtk-fsp in romstage ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Gerrit-Change-Number: 86015 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 00:18:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 00:18:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Jason-jh Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86027/comment/a5f44b95_eb824a53?us… : PS4, Line 13: ang when accessing DRAM. exceed 72 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 18 Jan 2025 00:10:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: CFR: Add min/max/step values and hex display flag for number options
by Angel Pons (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Filip Brozovic, Matt DeVillier, Sean Rhodes. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86039?usp=email ) Change subject: CFR: Add min/max/step values and hex display flag for number options ...................................................................... Patch Set 2: (5 comments) File src/commonlib/include/commonlib/cfr.h: https://review.coreboot.org/c/coreboot/+/86039/comment/40900226_1e3aebb4?us… : PS2, Line 94: * CFR_OPTFLAG_NUMBER_HEX: : * Displays a numeric option in hexadecimal instead of decimal notation. : * This flag is only valid for numeric options. Flags are meant to be applicable to all option types. This one is not. Instead of that, consider adding display format flags to the numeric option itself, which you have to modify anyway. https://review.coreboot.org/c/coreboot/+/86039/comment/55562134_1c02661f?us… : PS2, Line 139: uint32_t min; : uint32_t max; : uint32_t step; This changes the structure layout in a non-backwards compatible way. I can't recall if there is a version number anywhere, but there would need to be one. Are `min` and `max` inclusive or exclusive. It's easier to check if we have to limit the range when both values are inclusive (see .c comment) File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/86039/comment/ec09b62f_d732af9d?us… : PS2, Line 121: option->min = min; We should probably check that `min <= max` (both inclusive). https://review.coreboot.org/c/coreboot/+/86039/comment/ee3159eb_c43b7d05?us… : PS2, Line 122: 0xffffffff UINT32_MAX https://review.coreboot.org/c/coreboot/+/86039/comment/1b899414_571028da?us… : PS2, Line 123: step Let's assume a step size of 0 is equivalent to 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Gerrit-Change-Number: 86039 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 22:05:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: tree: Handle NULL pointer returned by smm_get_save_state()
by Jérémy Compostella (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Jeff Daly, Matt DeVillier, Vanessa Eusebio. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86040?usp=email ) Change subject: tree: Handle NULL pointer returned by smm_get_save_state() ...................................................................... tree: Handle NULL pointer returned by smm_get_save_state() Since commit 64d9e8568172402d8078c2c80ba994da16f4745b ("cpu/x86/smm_module_hander: Set up a save state map"), the smm_get_save_state() function can return a NULL pointer. Therefore, it is crucial to ensure that code properly handles the potential for a NULL pointer return value from smm_get_save_state(). Change-Id: Ie263393ca7d9d6b5e9868c5f73240fc788116cd0 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/amd/common/block/cpu/smm/smi_apmc.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 6 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/86040/1 diff --git a/src/soc/amd/common/block/cpu/smm/smi_apmc.c b/src/soc/amd/common/block/cpu/smm/smi_apmc.c index 9df6ae3..7c98405 100644 --- a/src/soc/amd/common/block/cpu/smm/smi_apmc.c +++ b/src/soc/amd/common/block/cpu/smm/smi_apmc.c @@ -33,6 +33,8 @@ /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { state = smm_get_save_state(core); + if (!state) + continue; smm_io_trap = state->smm_io_trap_offset; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index d2588cf..617ee10 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -176,6 +176,8 @@ /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); + if (!state) + continue; /* Check for Synchronous IO (bit0==1) */ if (!(state->io_misc_info & (1 << 0))) diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 99906d9..890167b 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -228,6 +228,8 @@ /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); + if (!state) + continue; /* Check for Synchronous IO (bit0 == 1) */ if (!(state->io_misc_info & (1 << 0))) diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 3bdc2a4..88d3e80 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -141,6 +141,8 @@ /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); + if (!state) + continue; /* Check for Synchronous IO (bit0==1) */ if (!(state->io_misc_info & (1 << 0))) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f1..b1a6a66 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -205,6 +205,8 @@ /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); + if (!state) + continue; /* Check for Synchronous IO (bit0 == 1) */ if (!(state->io_misc_info & (1 << 0))) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8caafb7..838b448 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -177,6 +177,8 @@ /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); + if (!state) + continue; /* Check for Synchronous IO (bit0 == 1) */ if (!(state->io_misc_info & (1 << 0))) -- To view, visit https://review.coreboot.org/c/coreboot/+/86040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie263393ca7d9d6b5e9868c5f73240fc788116cd0 Gerrit-Change-Number: 86040 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer
by Jérémy Compostella (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Arthur Heymans, Intel coreboot Reviewers. Hello Arthur Heymans, Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86038?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer ...................................................................... cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer The smm_get_save_state() function returns an invalid pointer (negative pointer) when the cpu variable is equal to the number of CPUs. This leads to a hang when the pointer is used to access the save state. TEST=No unexpected hangs in System Management Mode (SMM) were detected on fatcat. Change-Id: I09f969105190a004372c43cb1542f5b716da1eda Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/smm/smm_module_handler.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86038/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09f969105190a004372c43cb1542f5b716da1eda Gerrit-Change-Number: 86038 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[S] Change in coreboot[main]: CFR: Add min/max/step values and hex display flag for number options
by Filip Brozovic (Code Review) 17 Jan '25

17 Jan '25

Filip Brozovic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86039?usp=email ) Change subject: CFR: Add min/max/step values and hex display flag for number options ...................................................................... CFR: Add min/max/step values and hex display flag for number options This commit adds support for minimum/maximum limit values as well as step sizes for CFR number options. Additionally, add a new flag that specifies the option should be displayed in hexadecimal notation instead of decimal. Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Signed-off-by: Filip Brozovic <fbrozovic(a)gmail.com> --- M src/commonlib/include/commonlib/cfr.h M src/drivers/option/cfr.c M src/drivers/option/cfr_frontend.h 3 files changed, 20 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/86039/1 diff --git a/src/commonlib/include/commonlib/cfr.h b/src/commonlib/include/commonlib/cfr.h index 564c8a1..7ce1cbd 100644 --- a/src/commonlib/include/commonlib/cfr.h +++ b/src/commonlib/include/commonlib/cfr.h @@ -91,6 +91,9 @@ * this sets the EFI_VARIABLE_RUNTIME_ACCESS attribute. * It is out of scope of this specification how non runtime variables * are protected after the payload has hand over control. + * CFR_OPTFLAG_NUMBER_HEX: + * Displays a numeric option in hexadecimal instead of decimal notation. + * This flag is only valid for numeric options. */ enum cfr_option_flags { CFR_OPTFLAG_READONLY = 1 << 0, @@ -98,6 +101,7 @@ CFR_OPTFLAG_SUPPRESS = 1 << 2, CFR_OPTFLAG_VOLATILE = 1 << 3, CFR_OPTFLAG_RUNTIME = 1 << 4, + CFR_OPTFLAG_NUMBER_HEX = 1 << 5, }; struct __packed lb_cfr_varbinary { @@ -132,6 +136,9 @@ */ uint32_t flags; /* enum cfr_option_flags */ uint32_t default_value; + uint32_t min; + uint32_t max; + uint32_t step; /* * struct lb_cfr_varbinary opt_name * struct lb_cfr_varbinary ui_name diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c index 6d59ca9..09a32bf 100644 --- a/src/drivers/option/cfr.c +++ b/src/drivers/option/cfr.c @@ -104,8 +104,9 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t object_id, const char *opt_name, const char *ui_name, const char *ui_helptext, - uint32_t flags, uint32_t default_value, const struct sm_enum_value *values, - const uint64_t dep_id, const uint32_t *dep_values, const uint32_t num_dep_values) + uint32_t flags, uint32_t default_value, uint32_t min, uint32_t max, uint32_t step, + const struct sm_enum_value *values, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { struct lb_cfr_numeric_option *option = (struct lb_cfr_numeric_option *)current; size_t len; @@ -117,6 +118,9 @@ if (option->flags & (CFR_OPTFLAG_INACTIVE | CFR_OPTFLAG_VOLATILE)) option->flags |= CFR_OPTFLAG_READONLY; option->default_value = default_value; + option->min = min; + option->max = (min == 0 && max == 0) ? 0xffffffff : max; + option->step = step; option->size = sizeof(*option); current += option->size; @@ -148,7 +152,7 @@ { return write_numeric_option(current, CFR_TAG_OPTION_ENUM, object_id, sm_enum->opt_name, sm_enum->ui_name, sm_enum->ui_helptext, - sm_enum->flags, sm_enum->default_value, sm_enum->values, + sm_enum->flags, sm_enum->default_value, 0, 0, 0, sm_enum->values, dep_id, dep_values, num_dep_values); } @@ -159,8 +163,8 @@ { return write_numeric_option(current, CFR_TAG_OPTION_NUMBER, object_id, sm_number->opt_name, sm_number->ui_name, sm_number->ui_helptext, - sm_number->flags, sm_number->default_value, NULL, dep_id, - dep_values, num_dep_values); + sm_number->flags, sm_number->default_value, sm_number->min, sm_number->max, + sm_number->step, NULL, dep_id, dep_values, num_dep_values); } static uint32_t sm_write_opt_bool(char *current, const struct sm_obj_bool *sm_bool, @@ -170,7 +174,7 @@ { return write_numeric_option(current, CFR_TAG_OPTION_BOOL, object_id, sm_bool->opt_name, sm_bool->ui_name, sm_bool->ui_helptext, - sm_bool->flags, sm_bool->default_value, NULL, dep_id, + sm_bool->flags, sm_bool->default_value, 0, 0, 0, NULL, dep_id, dep_values, num_dep_values); } diff --git a/src/drivers/option/cfr_frontend.h b/src/drivers/option/cfr_frontend.h index 21c18e7..d83f18b 100644 --- a/src/drivers/option/cfr_frontend.h +++ b/src/drivers/option/cfr_frontend.h @@ -30,6 +30,9 @@ const char *ui_name; const char *ui_helptext; uint32_t default_value; + uint32_t min; + uint32_t max; + uint32_t step; }; struct sm_obj_bool { -- To view, visit https://review.coreboot.org/c/coreboot/+/86039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Gerrit-Change-Number: 86039 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com>

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[XS] Change in coreboot[main]: cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer
by Jérémy Compostella (Code Review) 17 Jan '25

17 Jan '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86038?usp=email ) Change subject: cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer ...................................................................... cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer The smm_get_save_state() function is incorrectly returning a pointer to the save state for a CPU that does not exit. This is leading to a hang when to pointer is used to access the save state. TEST=No unexpected hangs in System Management Mode (SMM) were detected on fatcat. Change-Id: I09f969105190a004372c43cb1542f5b716da1eda Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86038/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 899ee2f..d25b5f4 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -106,7 +106,7 @@ void *smm_get_save_state(int cpu) { - if (cpu > smm_runtime.num_cpus) + if (cpu >= smm_runtime.num_cpus) return NULL; return (void *)(smm_runtime.save_state_top[cpu] - diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 59489a4..49cc6aa 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -74,6 +74,8 @@ /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); + if (!state) + continue; io_misc_info = save_state_ops->get_io_misc_info(state); -- To view, visit https://review.coreboot.org/c/coreboot/+/86038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09f969105190a004372c43cb1542f5b716da1eda Gerrit-Change-Number: 86038 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: mb/starlabs/starbook: Add Alder Lake-N (N200) variant
by Felix Held (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Sean Rhodes. Felix Held has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85714?usp=email ) Change subject: mb/starlabs/starbook: Add Alder Lake-N (N200) variant ...................................................................... Patch Set 24: (1 comment) File src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb: PS24: shouldn't the 2 type c ports be on the CPU's tcss_xhci controller instead of on the PCH's xhci controller? at least that's what i remember from a half-finished coreboot port for adl-n that i've started some time ago -- To view, visit https://review.coreboot.org/c/coreboot/+/85714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Gerrit-Change-Number: 85714 Gerrit-PatchSet: 24 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 17 Jan 2025 18:09:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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