coreboot-gerrit January 2025

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Felix Held (Code Review) 17 Jan '25

17 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table Populate the PCI bridge IRQ routing table for Phoenix from the SMN registers to replace the stub implementation. The base addresses are copied from Genoa OpenSIL headers, which also correspond to Phoenix. TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. Before applying patch: [NOTE ] get_pci_routing_table stub: returning empty IRQ routing table [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist After applying patch: [DEBUG] 01.1: group: 0, swizzle: 0, irq: 0 [DEBUG] 01.2: group: 1, swizzle: 0, irq: 0 [DEBUG] 01.4: group: 0, swizzle: 2, irq: 2 [DEBUG] 01.5: group: 3, swizzle: 0, irq: 0 [DEBUG] 01.6: group: 4, swizzle: 0, irq: 0 [DEBUG] 02.5: group: 5, swizzle: 0, irq: 0 [DEBUG] 02.4: group: 0, swizzle: 1, irq: 2 [DEBUG] 01.3: group: 1, swizzle: 1, irq: 2 [DEBUG] 02.1: group: 2, swizzle: 2, irq: 3 [DEBUG] 02.2: group: 1, swizzle: 2, irq: 2 [DEBUG] 02.3: group: 3, swizzle: 2, irq: 1 [DEBUG] 02.6: group: 4, swizzle: 2, irq: 1 [DEBUG] 03.1: group: 2, swizzle: 0, irq: 0 [DEBUG] 03.2: group: 5, swizzle: 0, irq: 1 [DEBUG] 03.3: group: 5, swizzle: 2, irq: 1 [DEBUG] 03.4: group: 5, swizzle: 2, irq: 1 [DEBUG] 04.1: group: 2, swizzle: 2, irq: 1 [DEBUG] 08.1: group: 3, swizzle: 2, irq: 4 [DEBUG] 08.2: group: 4, swizzle: 2, irq: 4 [DEBUG] 08.3: group: 5, swizzle: 2, irq: 4 [DEBUG] PCI_CFG IRQ: Write PCI config space IRQ assignments [DEBUG] PCI_CFG IRQ: Finished writing PCI config space IRQ assignments Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85195 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/pci_irq_routing.c 1 file changed, 65 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/phoenix/pci_irq_routing.c b/src/soc/amd/phoenix/pci_irq_routing.c index 5c891c2..71202fa 100644 --- a/src/soc/amd/phoenix/pci_irq_routing.c +++ b/src/soc/amd/phoenix/pci_irq_routing.c @@ -1,14 +1,75 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/amd_pci_util.h> +#include <amdblocks/smn.h> #include <console/console.h> +#include <device/pci_def.h> #include <types.h> +#define MAX_BRIDGES 20 + +#define SMN_DEVICE_REMAP_BASE_ADDR 0x13b100b8 +#define SMN_PCI_INTERRUPT_ROUTING_BASE_ADDR 0x14300040 + +union iohc_nb_prog_device_remap { + struct { + uint32_t fn_num : 3; /* [ 2.. 0] */ + uint32_t dev_num : 5; /* [ 7.. 3] */ + uint32_t : 24; /* [31.. 8] */ + }; + uint32_t raw; +}; + +union ioapic_br_irq_routing { + struct { + uint32_t intr_grp : 3; /* [ 2.. 0] */ + uint32_t : 1; /* [ 3.. 3] */ + uint32_t intr_swz : 2; /* [ 5.. 4] */ + uint32_t : 10; /* [15.. 6] */ + uint32_t intr_map : 5; /* [20..16] */ + uint32_t : 11; /* [31..21] */ + }; + uint32_t raw; +}; + const struct pci_routing_info *get_pci_routing_table(size_t *entries) { - /* TODO: still needs to be implemented for the non-FSP case */ - printk(BIOS_NOTICE, "%s stub: returning empty IRQ routing table\n", __func__); + static bool table_initialized; + static struct pci_routing_info routing_table[MAX_BRIDGES]; - *entries = 0; - return NULL; + union iohc_nb_prog_device_remap dev_remap; + union ioapic_br_irq_routing ioapic_routing; + + if (table_initialized) { + *entries = MAX_BRIDGES; + return routing_table; + } + + /* + * For Phoenix, the logical and physical bridge numbers map 1:1, which may not be + * the case for other SoCs. + */ + for (size_t i = 0; i < MAX_BRIDGES; ++i) { + dev_remap.raw = smn_read32(SMN_DEVICE_REMAP_BASE_ADDR + + sizeof(uint32_t) * i); + routing_table[i].devfn = (dev_remap.dev_num << 3) | dev_remap.fn_num; + } + + for (size_t i = 0; i < MAX_BRIDGES; ++i) { + ioapic_routing.raw = smn_read32(SMN_PCI_INTERRUPT_ROUTING_BASE_ADDR + + sizeof(uint32_t) * i); + routing_table[i].group = ioapic_routing.intr_grp; + routing_table[i].swizzle = ioapic_routing.intr_swz; + routing_table[i].bridge_irq = ioapic_routing.intr_map; + printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n", + PCI_SLOT(routing_table[i].devfn), + PCI_FUNC(routing_table[i].devfn), + routing_table[i].group, + routing_table[i].swizzle, + routing_table[i].bridge_irq); + } + table_initialized = true; + + *entries = MAX_BRIDGES; + return routing_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer
by Felix Held (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Nicholas Chin. Felix Held has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85790?usp=email ) Change subject: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer ...................................................................... Patch Set 5: (1 comment) File util/find_usbdebug/find_usbdebug.sh: https://review.coreboot.org/c/coreboot/+/85790/comment/adb374fa_e9fb915f?us… : PS5, Line 50: should be a tab instead of spaces -- To view, visit https://review.coreboot.org/c/coreboot/+/85790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff Gerrit-Change-Number: 85790 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 17:51:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: acpi: Guard CBMEM driver against Chrome devices
by Felix Held (Code Review) 17 Jan '25

17 Jan '25

Felix Held has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81029?usp=email ) Change subject: acpi: Guard CBMEM driver against Chrome devices ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: thanks for this fix; much better solution compared to my attempt here CB:81264 -- To view, visit https://review.coreboot.org/c/coreboot/+/81029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76 Gerrit-Change-Number: 81029 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 17 Jan 2025 17:47:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Felix Held (Code Review) 17 Jan '25

17 Jan '25

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Abandoned CB:81029 is a better solution -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Hello Angel Pons, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85767?usp=email to look at the new patch set (#7). Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... mb/asus: Add Maximus VI Gene (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - DIMM_B1 and DIMM_B2 DDR3/DDR3L DIMM slots (DIMM_A1 and DIMM_A2 also not working on vendor firmware, assuming hardware defect) - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel ASMedia USB 3.0 Ports - Both back panel USB 3.0 Ports - USB 3.0 Header - USB 2.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x4 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) - ASUS mPCIe Combo II connector not (yet) tested: - ASUS Extension Board - Optical S/PDIF out not (yet) working: - S3 suspend and resume - Various LEDs (cosmetical) - Both SATA3 6.0 GB/s connectors by ASMedia (fix will soon be merged) Change-Id: I31029c78cba65cad96718132235c140c3997c815 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_gene/Kconfig A src/mainboard/asus/maximus_vi_gene/Kconfig.name A src/mainboard/asus/maximus_vi_gene/Makefile.mk A src/mainboard/asus/maximus_vi_gene/acpi/ec.asl A src/mainboard/asus/maximus_vi_gene/acpi/platform.asl A src/mainboard/asus/maximus_vi_gene/acpi/superio.asl A src/mainboard/asus/maximus_vi_gene/board_info.txt A src/mainboard/asus/maximus_vi_gene/bootblock.c A src/mainboard/asus/maximus_vi_gene/data.vbt A src/mainboard/asus/maximus_vi_gene/devicetree.cb A src/mainboard/asus/maximus_vi_gene/dsdt.asl A src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads A src/mainboard/asus/maximus_vi_gene/gpio.c A src/mainboard/asus/maximus_vi_gene/hda_verb.c A src/mainboard/asus/maximus_vi_gene/romstage.c 15 files changed, 550 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85767/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 7 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Hello Angel Pons, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85767?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... mb/asus: Add Maximus VI Gene (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - DIMM_B1 and DIMM_B2 DDR3/DDR3L DIMM slots (DIMM_A1 and DIMM_A2 also not working on vendor firmware, assuming hardware defect) - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel ASMedia USB 3.0 Ports - Both back panel USB 3.0 Ports - USB 3.0 Header - USB 2.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x4 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) - ASUS mPCIe Combo II connector not (yet) tested: - ASUS Extension Board - Optical S/PDIF out not (yet) working: - S3 suspend and resume - Various LEDs (cosmetical) - Both SATA3 6.0 GB/s connectors by ASMedia (fix will soon be merged) Change-Id: I31029c78cba65cad96718132235c140c3997c815 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_gene/Kconfig A src/mainboard/asus/maximus_vi_gene/Kconfig.name A src/mainboard/asus/maximus_vi_gene/Makefile.mk A src/mainboard/asus/maximus_vi_gene/acpi/ec.asl A src/mainboard/asus/maximus_vi_gene/acpi/platform.asl A src/mainboard/asus/maximus_vi_gene/acpi/superio.asl A src/mainboard/asus/maximus_vi_gene/board_info.txt A src/mainboard/asus/maximus_vi_gene/bootblock.c A src/mainboard/asus/maximus_vi_gene/data.vbt A src/mainboard/asus/maximus_vi_gene/devicetree.cb A src/mainboard/asus/maximus_vi_gene/dsdt.asl A src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads A src/mainboard/asus/maximus_vi_gene/gpio.c A src/mainboard/asus/maximus_vi_gene/hda_verb.c A src/mainboard/asus/maximus_vi_gene/romstage.c 15 files changed, 550 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85767/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 6 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: cpu/x86/topology: Fix FSP-S crash caused by shared core ID
by Jérémy Compostella (Code Review) 17 Jan '25

17 Jan '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86004?usp=email ) Change subject: cpu/x86/topology: Fix FSP-S crash caused by shared core ID ...................................................................... cpu/x86/topology: Fix FSP-S crash caused by shared core ID This resolves a crash issue observed on Meteor Lake and introduced by commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: Simplify CPU topology initialization"). This commit simplifies the code and provides more detailed CPU topology information by generalizing the use of the Extended Topology Enumeration Leaves 0x1f. As a result, the coreboot APIC core_id field does not provide the fully detailed path information. It turns out that the topology core identifier is used by the coreboot MP service mp_get_processor_info() implementation. But the MP Service EFI_CPU_PHYSICAL_LOCATION data structure only captures information about the package, core, and thread. The core identifier returned to the MP service caller must incorporate the full hierarchical path (die group, die, module, tile, module and core). This commit adds a new field to the cpu topology structure to represent the core ID within the package. For reference, here is that signature of the crash: LAPIC 0x40 in X2APIC mode. CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 [...] The crash occurred when FSP attempted to lock the Protected Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL 0x4e). 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx 69f3d1e5: 0f 30 wrmsr 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 FSP experiences issues due to attempting to lock the same register multiple times for a single core. This is caused by an inconsistency in the processor information data structure, where multiple cores share the same identifier. This is not permitted and triggers a General Protection Fault Exception. TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex board. Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86004 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Cliff Huang <cliff.huang(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhixing Ma <zhixing.ma(a)intel.com> --- M src/cpu/x86/topology.c M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/include/device/path.h 3 files changed, 11 insertions(+), 1 deletion(-) Approvals: Cliff Huang: Looks good to me, but someone else must approve build bot (Jenkins): Verified Zhixing Ma: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index 58e71fc..70bdf47 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -110,6 +110,7 @@ static struct bitfield_descriptor topology[LEVEL_TYPE_MAX]; static enum cb_err ret; static bool done; + unsigned int core_id_within_package; struct { unsigned int level; unsigned int *field; @@ -151,4 +152,8 @@ *apic_fields[i].field = value; } } + + core_id_within_package = apicid & ((1 << topology[LEVEL_TYPE_PACKAGE].first_bit) - 1); + core_id_within_package >>= topology[LEVEL_TYPE_CORE].first_bit; + cpu->path.apic.core_id_within_package = core_id_within_package; } diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 41fccd6..b697ccb 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -61,7 +61,7 @@ processor_info_buffer->ProcessorId = dev->path.apic.apic_id; processor_info_buffer->Location.Package = dev->path.apic.package_id; - processor_info_buffer->Location.Core = dev->path.apic.core_id; + processor_info_buffer->Location.Core = dev->path.apic.core_id_within_package; processor_info_buffer->Location.Thread = dev->path.apic.thread_id; return FSP_SUCCESS; diff --git a/src/include/device/path.h b/src/include/device/path.h index fdc2f44..03aa909 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -82,6 +82,11 @@ unsigned int core_id; unsigned int thread_id; unsigned int module_id; + /* + * Core identifier within the package, including the die group, die, tile, module, and + * specific core. + */ + unsigned int core_id_within_package; unsigned char core_type; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Gerrit-Change-Number: 86004 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Name of user not set #1005776 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jason-jh Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Jason-jh Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86027/comment/d4ff1c94_d2ca6711?us… : PS3, Line 12: request > requests Done https://review.coreboot.org/c/coreboot/+/86027/comment/5a3c0240_f6367a76?us… : PS3, Line 14: Otherwise, GCE will hang when accessing DRAM. > Move the first few words to the previous line Done File src/soc/mediatek/mt8196/mminfra.c: https://review.coreboot.org/c/coreboot/+/86027/comment/b59b6eac_cbdd9a37?us… : PS3, Line 35: 0x1 > Maybe just `1` for consistency? But other places in this file also use Hex for the non-zreo settings. So I think `0x1` should be consistent in this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 15:40:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jason-jh Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Jason-jh Lin, Yidi Lin. Jason-jh Lin has uploaded a new patch set (#4) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... soc/mediatek/mt8196: Add GCE ddren sel control to mminfra MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction ACK from SPM: 0, non-SPM: 0x1. In MT8196, SPM has masked all the DDR requests, so this setting should be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will hang when accessing DRAM. BUG=b:379039600 TEST=boot up ok, GCE can access DRAM continuously Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Signed-off-by: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/mminfra.h M src/soc/mediatek/mt8196/mminfra.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Drop xhci_overcurrent_mapping
by Keith Hui (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Intel coreboot Reviewers. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85925?usp=email ) Change subject: sb/intel/bd82x6x: Drop xhci_overcurrent_mapping ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I ran the train through mb/asus/p8z77-m and my USB 3 ports still work. -- To view, visit https://review.coreboot.org/c/coreboot/+/85925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28 Gerrit-Change-Number: 85925 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 15:29:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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