coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/rauru: Add panel driver in mainboard
by Jarried Lin (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Bincai Liu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85951?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/rauru: Add panel driver in mainboard ...................................................................... mb/google/rauru: Add panel driver in mainboard Add panel driver in mainboard for rauru project and support OLED eDP panel. TEST=check edp training pass and show log: EQ training pass BUG=b:343351631 Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/Makefile.mk M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h A src/mainboard/google/rauru/panel.c A src/mainboard/google/rauru/panel.h A src/mainboard/google/rauru/panel_oled.c 8 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85951/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Gerrit-Change-Number: 85951 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Add DVFS support in romstage
by Jarried Lin (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86042?usp=email ) Change subject: mb/google/rauru: Add DVFS support in romstage ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rauru/romstage.c: https://review.coreboot.org/c/coreboot/+/86042/comment/d0a8deb0_a77e6aae?us… : PS4, Line 46: dvfs_init(); > Just to confirm, this needs to run *after* the kraken driver (loading pi_img) in `mtk_fsp_load_and_r […] Hi Yu-ping, Kraken runs during the ramstage load, so we just need to ensure initialization DVFS before that. -- To view, visit https://review.coreboot.org/c/coreboot/+/86042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f290946365b4c5a650651ebea30ffc76583d2b2 Gerrit-Change-Number: 86042 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 09:25:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: vc/intel/fsp/twinlake: Update FSP headers to v5222.01
by Alok Agarwal (Code Review) 20 Jan '25

20 Jan '25

Alok Agarwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86062?usp=email ) Change subject: vc/intel/fsp/twinlake: Update FSP headers to v5222.01 ...................................................................... vc/intel/fsp/twinlake: Update FSP headers to v5222.01 - Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:354612775 TEST=Able to build and boot google/Tivviks * vc/intel/fsp/twinlake: Update FSP headers to v5222.01 - Add EnableTcssCovTypeA and MappingPchXhciUsbA in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:390225562 TEST=Able to build and boot google/Tivviks Change-Id: Ibd1a289ddd9d434fabe3956e4edaf648f4403bf7 Signed-off-by: alokagarwal <alok.agarwal(a)intel.corp-partner.google.com> --- M src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86062/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h index add6425..c218dc1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h @@ -3856,7 +3856,18 @@ /** Offset 0x0F96 - Reserved **/ - UINT8 Reserved53[16]; + UINT8 Reserved53[8]; + +/** Offset 0x0F9E - Type C Port x Convert to TypeA + Enable / Disable(default) Type C Port x Convert to TypeA + $EN_DIS +**/ + UINT8 EnableTcssCovTypeA[4]; + +/** Offset 0x0FA2 - PCH xhci port x for Type C Port x mapping + input PCH xhci port x for Type C Port 0 mapping. +**/ + UINT8 MappingPchXhciUsbA[4]; /** Offset 0x0FA6 - FOMS Control Policy Choose the Foms Control Policy, <b>Default = 0 </b> -- To view, visit https://review.coreboot.org/c/coreboot/+/86062?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd1a289ddd9d434fabe3956e4edaf648f4403bf7 Gerrit-Change-Number: 86062 Gerrit-PatchSet: 1 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Naresh Solanki (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Felix Held, Jérémy Compostella. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/85639/comment/5442298b_a13de451?us… : PS1, Line 280: uint8_t > please don't mark this as resolved when it hasn't been resolved yet to make sure that this doesn't g […] Since its purpose is to uniquely identify a particular cache, I feel cache_id should be fine & please let me know if you have better suggestion. Yes, Will update to uint16_t . -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 20 Jan 2025 09:10:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 10: Code-Review+2 (2 comments) File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86017/comment/2f4261e0_abb726f3?us… : PS8, Line 234: int i; > size_t Acknowledged https://review.coreboot.org/c/coreboot/+/86017/comment/1786dda8_cfdce0ad?us… : PS8, Line 268: int i; > size_t Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 09:04:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Zhaoqing Jiu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Zhaoqing Jiu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 10: (14 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86017/comment/00160cf8_15adc8c2?us… : PS8, Line 9: Add thermal driver to support LVTS (Low Voltage Thermal Sensor). > This seems new for MT8196. The other SOC do not have such a driver. […] The other SOC also have such driver, but only have kernel part. For MT8196, moved driver port of driver initialization to coreboot. https://review.coreboot.org/c/coreboot/+/86017/comment/b521367d_1fc916bd?us… : PS8, Line 10: > Why is a separate SRAM driver needed? SRAM is used to communicate with micro process, set default value in coreboot. https://review.coreboot.org/c/coreboot/+/86017/comment/b9f78edc_13bf70e0?us… : PS8, Line 11: TEST=Check temperatures read from each sensors. > With the command `sensors`? Just check the coreboot log Commit Message: https://review.coreboot.org/c/coreboot/+/86017/comment/21f09105_bee02247?us… : PS9, Line 12: [0m > Remove these control codes. Done File src/soc/mediatek/mt8196/include/soc/thermal_internal.h: https://review.coreboot.org/c/coreboot/+/86017/comment/12c3b40d_e7458fc1?us… : PS8, Line 15: /* > Add a blank line above? Done https://review.coreboot.org/c/coreboot/+/86017/comment/42b5ff33_3f5b7537?us… : PS8, Line 16: * module LVTS Plan > Move *LVTS Plan* more to the right? Done File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86017/comment/5ddb0fc9_dc428dca?us… : PS8, Line 38: */ > Please remove the duplicate comments in thermal_internal.h. Done https://review.coreboot.org/c/coreboot/+/86017/comment/aae3870e_3f11449d?us… : PS8, Line 163: printk(BIOS_INFO, "%s: msr_raw=%u, temp_mc=%d\n", __func__, msr_raw, temp_mc); > Please change to `BIOS_DEBUG` Done https://review.coreboot.org/c/coreboot/+/86017/comment/5db01075_d6715396?us… : PS8, Line 170: uint32_t i; > I'd prefer using `int` for array index. `size_t` is for representing the size of a C object. […] Done https://review.coreboot.org/c/coreboot/+/86017/comment/a026aa92_ef554e80?us… : PS8, Line 271: printk(BIOS_INFO, "%s\n", __func__); > Can we remove this log? Done https://review.coreboot.org/c/coreboot/+/86017/comment/351f0f8c_34a26abf?us… : PS8, Line 375: * to wait HW init done, > to wait *until* HW init *is* done, Done https://review.coreboot.org/c/coreboot/+/86017/comment/dacbd75b_4f581852?us… : PS8, Line 376: translates > translate Done https://review.coreboot.org/c/coreboot/+/86017/comment/75658676_cad07b30?us… : PS8, Line 379: finish > finishes Done https://review.coreboot.org/c/coreboot/+/86017/comment/cb464aec_08fa7d6a?us… : PS8, Line 373: * 26111 is magic num : * this is to keep system alive for a while : * to wait HW init done, : * because 0 msr raw will translates to 28x'C : * and then 28x'C will trigger a SW reset. : * : * if HW init finish, this msr raw will not be 0, : * system can report normal temperature. : * if wait over 60 times zero, this means something : * wrong with HW, must trigger BUG on and dump useful : * register for debug. > Re-flow the text? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 09:01:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add panel driver in mainboard
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85951?usp=email ) Change subject: mb/google/rauru: Add panel driver in mainboard ...................................................................... Patch Set 7: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85951/comment/cb5eccde_d8e9a8d5?us… : PS7, Line 9: ruaru rauru https://review.coreboot.org/c/coreboot/+/85951/comment/d889e749_287a07a0?us… : PS7, Line 9: oled OLED File src/mainboard/google/rauru/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85951/comment/bc4f0701_a6592e5d?us… : PS7, Line 15: ramstage-y += mainboard.c sort File src/mainboard/google/rauru/panel.h: https://review.coreboot.org/c/coreboot/+/85951/comment/067e73c4_d2299148?us… : PS7, Line 3: KUKUI RAURU https://review.coreboot.org/c/coreboot/+/85951/comment/10c48801_7bd324ec?us… : PS7, Line 8: #endif /* __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ */ > `adding a line without newline at end of file` Please fix. https://review.coreboot.org/c/coreboot/+/85951/comment/64bf36c1_49ddf4b8?us… : PS7, Line 8: KUKUI RAURU -- To view, visit https://review.coreboot.org/c/coreboot/+/85951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Gerrit-Change-Number: 85951 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 08:59:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin, Jitao Shi, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 7: (30 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85949/comment/9e4b1cce_1949b817?us… : PS2, Line 10: traning > Do you mean `training`? Acknowledged https://review.coreboot.org/c/coreboot/+/85949/comment/6868c607_48279676?us… : PS2, Line 11: > Please mention what DVO is in the commit message. Done File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/0ad7c2b4_9952687e?us… : PS2, Line 99: gs_level > not done Done File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/7c15959a_d563190d?us… : PS6, Line 32: const struct mtk_dvo_sync_param *sync) > will fix next patchset Done File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/a924af6b_f23a4a80?us… : PS7, Line 95: 0x20 `0x20 << EXT_TG_DLY_LINE` https://review.coreboot.org/c/coreboot/+/85949/comment/92c4e99a_a9978ff3?us… : PS7, Line 100: if (dvo->gs_level >= MTK_DVO_GSL_MAX) : return; `assert(dvo->gs_level < MTK_DVO_GSL_MAX)` https://review.coreboot.org/c/coreboot/+/85949/comment/2c415ab8_49a8df17?us… : PS7, Line 181: .regs_ck = (void *)CKSYS_GP2_BASE, : .regs_mm = (void *)MMSYS1_CONFIG_BASE, Remove these two unused fields from here and the header. https://review.coreboot.org/c/coreboot/+/85949/comment/b3622ba3_7d2c61cd?us… : PS7, Line 191: mtk_dpintf_power_on Now this name becomes inconsistent with other function names in this file. From your commit message, "DISP_DVO is a highly advanced variant of DP_INTF". Therefore I think it's fine to use "dvo" in the function name. Could you please change it back? File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/cc2b637f_b6b73c80?us… : PS4, Line 54: u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE]) > will fix next patchset Done File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/225c44c6_6295f5e1?us… : PS7, Line 52: u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE]) align https://review.coreboot.org/c/coreboot/+/85949/comment/0c52aa20_5747806c?us… : PS7, Line 70: DP_TRAIN_VOLTAGE_SWING_LEVEL_3 DPTX_SWING3 https://review.coreboot.org/c/coreboot/+/85949/comment/9d997953_4662d1a6?us… : PS7, Line 269: linkrate = mtk_dp->train_info.linkrate; : lanecount = mtk_dp->train_info.linklane_count; This is wrong. By the time we reach here, `mtk_dp->train_info.*` haven't been set yet. Please remove these. https://review.coreboot.org/c/coreboot/+/85949/comment/a090a9ee_3819df70?us… : PS7, Line 370: int mtk_edp_init(struct mtk_dp *mtk_dp,struct edid *edid) > `space required after that ',' (ctx:VxV)` Please fix. https://review.coreboot.org/c/coreboot/+/85949/comment/6a9df618_b2612fc8?us… : PS7, Line 374: 0xFF000000 Please confirm if this is supposed to be 0xFF000000 or 0x80000000. https://review.coreboot.org/c/coreboot/+/85949/comment/776863ec_6cc79d4d?us… : PS7, Line 376: m u https://review.coreboot.org/c/coreboot/+/85949/comment/4a8dcee4_d0aeda59?us… : PS7, Line 393: %s `%s: Failed to ...` File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/a39a2e91_708ec074?us… : PS4, Line 142: switch (value) { > will fix next patchset Done File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/dae8d545_e0448838?us… : PS7, Line 106: mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, 0x18); : mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, 0x6); Can we merge these into a single call? ``` mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK); ``` Also remove `{}` for the "for loop". https://review.coreboot.org/c/coreboot/+/85949/comment/529f59fb_86cb8ac9?us… : PS7, Line 290: dptx_hal_reset_swing_preemphasis_mt8196 How about `dptx_hal_swing_emp_reset` (to be consistent with `dptx_hal_phyd_reset` below)? File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/7d847483_ab1ee72d?us… : PS6, Line 137: 0x6c > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/52698015_a736c4a8?us… : PS6, Line 141: c > will fix next patchset Done File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/6794f69d_dc683556?us… : PS4, Line 112: #define HACT_SHIFT 16 > align Done https://review.coreboot.org/c/coreboot/+/85949/comment/a48bafb7_c36e03cb?us… : PS4, Line 124: #define VACT_SHIFT 16 > will fix next patchset Done File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/5309e1f6_0ec64496?us… : PS2, Line 199: gs_level > will be used in mt8196/dp_intf. […] Done File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/ae9a392d_25f8c168?us… : PS7, Line 32: u8 *preemphasis); align File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/7072ece3_34935ef9?us… : PS4, Line 26: pre_emphasis > will be fix next patch Done https://review.coreboot.org/c/coreboot/+/85949/comment/fc3b46ca_eafe7f1d?us… : PS4, Line 31: pre_emphasis > will be fix next patch. Done https://review.coreboot.org/c/coreboot/+/85949/comment/42559bfa_3458e87d?us… : PS4, Line 32: pre_emphasis > will be fix next patch Done File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/5d58daf5_66e4f402?us… : PS2, Line 38: void mtk_edp_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp); : void mtk_edp_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable); : void mtk_edp_set_swing_pre_emphasis > will be change to dptx_hal_ next patchset Done File src/soc/mediatek/mt8196/include/soc/dptx_reg.h: https://review.coreboot.org/c/coreboot/+/85949/comment/4f55888e_672bda9f?us… : PS7, Line 198: DP_TRAIN_VOLTAGE_SWING_LEVEL_3 Also duplicate of `DPTX_SWING3`. -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 08:56:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable SAGv
by Subrata Banik (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Bora Guvendik, Pranava Y N. Subrata Banik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/85272?usp=email ) Change subject: mb/google/fatcat: Enable SAGv ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b Gerrit-Change-Number: 85272 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 08:51:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Zhaoqing Jiu. Hello Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86017?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... soc/mediatek/mt8196: Add thermal driver Add thermal driver to support LVTS (Low Voltage Thermal Sensor). BUG=b:317009620 TEST=Check temperatures read from each sensors. [INFO ] [LVTS_MSR] ts0 msr_all=14104, msr_temp=16644, temp=35694 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 35694 rg_temp 35697(36554) [INFO ] [LVTS_MSR] ts1 msr_all=14116, msr_temp=16662, temp=36088 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 36088 rg_temp 36091(36958) [INFO ] [LVTS_MSR] ts2 msr_all=140f6, msr_temp=16630, temp=35387 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 35387 rg_temp 35390(36240) [INFO ] [LVTS_MSR] ts3 msr_all=14105, msr_temp=16645, temp=35716 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 35716 rg_temp 35718(36576) [INFO ] [LVTS_MSR] ts4 msr_all=14129, msr_temp=16681, temp=36504 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 36504 rg_temp 36507(37384) [INFO ] [LVTS_MSR] ts5 msr_all=1412d, msr_temp=16685, temp=36592 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 36592 rg_temp 36595(37474) [INFO ] [LVTS_MSR] ts6 msr_all=140eb, msr_temp=16619, temp=35146 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 35146 rg_temp 35149(35993) [INFO ] [LVTS_MSR] ts7 msr_all=14126, msr_temp=16678, temp=36438 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 36438 rg_temp 36442(37317) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/thermal.h A src/soc/mediatek/mt8196/include/soc/thermal_internal.h A src/soc/mediatek/mt8196/thermal.c A src/soc/mediatek/mt8196/thermal_sram.c 7 files changed, 1,008 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86017/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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