coreboot-gerrit January 2025

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.1
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.1 ...................................................................... soc/mediatek/mt8196: Update MCUPM firmware to v1.1 Change to use release branch. TEST=NA BUG=b:317009620 Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Signed-off-by: Agogo Huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mcupm.bin M soc/mediatek/mt8196/mcupm.bin.md5 M soc/mediatek/mt8196/mcupm_release_notes.txt 3 files changed, 6 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Verified; Looks good to me, approved diff --git a/soc/mediatek/mt8196/mcupm.bin b/soc/mediatek/mt8196/mcupm.bin index df4ea8f..74511bc 100644 --- a/soc/mediatek/mt8196/mcupm.bin +++ b/soc/mediatek/mt8196/mcupm.bin Binary files differ diff --git a/soc/mediatek/mt8196/mcupm.bin.md5 b/soc/mediatek/mt8196/mcupm.bin.md5 index a30b9f0..516b6cb 100644 --- a/soc/mediatek/mt8196/mcupm.bin.md5 +++ b/soc/mediatek/mt8196/mcupm.bin.md5 @@ -1 +1 @@ -5b8708510dc7d2f305791fdf286c2d42 *mcupm.bin +ce38fc137fc836aad29e87da328e6822 *mcupm.bin diff --git a/soc/mediatek/mt8196/mcupm_release_notes.txt b/soc/mediatek/mt8196/mcupm_release_notes.txt index f3b09fd..fc1e033 100644 --- a/soc/mediatek/mt8196/mcupm_release_notes.txt +++ b/soc/mediatek/mt8196/mcupm_release_notes.txt @@ -2,3 +2,8 @@ # Version 1.0 1. Initial release. +2. Base on MTK dev branch. + +# Version 1.1 +1. Change to use MTK release branch. +2. Improve the CPU frequency to 3.6 GHz. -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 4 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.1
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Yidi Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.1 ...................................................................... Patch Set 4: Verified+1 -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 4 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:34:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.1
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Yidi Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.1 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 4 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.1
by agogo (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Yidi Lin, Yu-Ping Wu. agogo has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.1 ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/blobs/+/85980/comment/6ffb04fc_76fa27bb?usp=e… : PS3, Line 7: > to Done https://review.coreboot.org/c/blobs/+/85980/comment/8920d802_f9245e77?usp=e… : PS3, Line 7: Add > Update Done https://review.coreboot.org/c/blobs/+/85980/comment/3e4c121c_d486e46f?usp=e… : PS3, Line 9: Change to use release branch > Add `. […] Done File soc/mediatek/mt8196/mcupm_release_notes.txt: https://review.coreboot.org/c/blobs/+/85980/comment/e4048e9b_0bb7141b?usp=e… : PS3, Line 7: 1. Change to use release branch > Better to also explain the functional difference from v1. […] Done -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 4 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:21:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.1
by agogo (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Yidi Lin, agogo. Hello Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85980?usp=email to look at the new patch set (#4). Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.1 ...................................................................... soc/mediatek/mt8196: Update MCUPM firmware to v1.1 Change to use release branch. TEST=NA BUG=b:317009620 Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Signed-off-by: Agogo Huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mcupm.bin M soc/mediatek/mt8196/mcupm.bin.md5 M soc/mediatek/mt8196/mcupm_release_notes.txt 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/85980/4 -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 4 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Zhaoqing Jiu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Zhaoqing Jiu has uploaded a new patch set (#9) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... soc/mediatek/mt8196: Add thermal driver Add thermal driver to support LVTS (Low Voltage Thermal Sensor). TEST=Check temperatures read from each sensors. [0m[INFO ] [LVTS_MSR] ts0 msr_all=14104, msr_temp=16644, temp=35694 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 35694 rg_temp 35697(36554) [0m [0m[INFO ] [LVTS_MSR] ts1 msr_all=14116, msr_temp=16662, temp=36088 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 36088 rg_temp 36091(36958) [0m [0m[INFO ] [LVTS_MSR] ts2 msr_all=140f6, msr_temp=16630, temp=35387 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 35387 rg_temp 35390(36240) [0m [0m[INFO ] [LVTS_MSR] ts3 msr_all=14105, msr_temp=16645, temp=35716 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 35716 rg_temp 35718(36576) [0m [0m[INFO ] [LVTS_MSR] ts4 msr_all=14129, msr_temp=16681, temp=36504 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 36504 rg_temp 36507(37384) [0m [0m[INFO ] [LVTS_MSR] ts5 msr_all=1412d, msr_temp=16685, temp=36592 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 36592 rg_temp 36595(37474) [0m [0m[INFO ] [LVTS_MSR] ts6 msr_all=140eb, msr_temp=16619, temp=35146 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 35146 rg_temp 35149(35993) [0m [0m[INFO ] [LVTS_MSR] ts7 msr_all=14126, msr_temp=16678, temp=36438 [0m [0m[INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 36438 rg_temp 36442(37317) BUG=b:317009620 Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/thermal.h A src/soc/mediatek/mt8196/include/soc/thermal_internal.h A src/soc/mediatek/mt8196/thermal.c A src/soc/mediatek/mt8196/thermal_sram.c 7 files changed, 1,033 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86017/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 5: (2 comments) File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/64bf6fe8_c5a12033?us… : PS1, Line 18: RTC_BBPU_PWREN = BIT(0), > The new version of the header file mt6685_RTC_HW.H deletes the same macro definition as rtc_common. […] Sorry, but I'm not quite convinced of that approach. The duplicate constants are one problem, but the underlying problem is the organization of the headers. In PS5 the `RTC_*` constants are still spread in rtc.h and mt6685_rtc_hw.h in MT8196's code (not considering the common rtc_reg_common.h), and it's unclear to me what the difference of them is. I asked about the distinction of rtc.h, mt6685_rtc_hw.h and mt6685_rtc.h, but you didn't answer my question yet. In PS5 you removed the duplicate constants in mt6685_rtc_hw.h. However that leaves mt6685_rtc_hw.h in an incomplete state (for example it contains `RTC_BBPU_PWREN` but not `RTC_BBPU`), so that approach is not ideal. Considering the limited time we have, I'd like to propose a simplest approach: following what we did for existing SoCs. - Remove mt6685_hw.h, mt6685_rtc_hw.h and mt6685_rtc.h and keep only rtc.h. Move constants from these headers to rtc.h if they are used. - Keep only required constants in rtc.h. Please make sure we don't have duplicate constants in rtc.h, rtc_common.h and rtc_reg_common.h. Then we may consider refactoring in future patches. File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/3ac1ac4a_18306f6e?us… : PS2, Line 358: rtc_init_after_recovery > move to above line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 06:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/siemens/mc_ehl{2...5}: Fix return in variant_mainboard_final()
by Werner Zeh (Code Review) 19 Jan '25

19 Jan '25

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85891?usp=email ) Change subject: mb/siemens/mc_ehl{2...5}: Fix return in variant_mainboard_final() ...................................................................... mb/siemens/mc_ehl{2...5}: Fix return in variant_mainboard_final() If no resource is found for a device, do not return directly, otherwise the following code will no longer be executed. Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85891 Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c 4 files changed, 32 insertions(+), 32 deletions(-) Approvals: Werner Zeh: Looks good to me, approved build bot (Jenkins): Verified Uwe Poeche: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index ac3ab14..b384619 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -42,22 +42,21 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - disable_sdr_modes(res); + if (res) + disable_sdr_modes(res); } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c index d76ac03..c68ecda 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c @@ -33,13 +33,14 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c index 3ef72fd..64cb3f3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c @@ -32,12 +32,13 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c index ac3ab14..b384619 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c @@ -42,22 +42,21 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - disable_sdr_modes(res); + if (res) + disable_sdr_modes(res); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6 Gerrit-Change-Number: 85891 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl2: Limit eMMC speed mode to DDR50
by Werner Zeh (Code Review) 19 Jan '25

19 Jan '25

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85881?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl2: Limit eMMC speed mode to DDR50 ...................................................................... mb/siemens/mc_ehl2: Limit eMMC speed mode to DDR50 Due to layout restrictions on mc_ehl2, the eMMC interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the eMMC controller to DDR50 mode only so that the eMMC driver in OS will choose the right mode for operation even if the attached eMMC card supports higher modes. BUG=none TEST=Boot into Linux and check dmesg output for mmc modes Change-Id: I668bb5b0b3197497920b36bcf283c25d2a0c00ba Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85881 Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Uwe Poeche: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index dd90d6f..ac3ab14 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -50,6 +50,15 @@ /* Use preset driver strength from preset value registers. */ clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); } + + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + if (dev) { + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + disable_sdr_modes(res); + } } static void finalize_boot(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/85881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I668bb5b0b3197497920b36bcf283c25d2a0c00ba Gerrit-Change-Number: 85881 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/siemens/mc_ehl{2...4}: Simplify SD code as well as for mc_ehl5
by Werner Zeh (Code Review) 19 Jan '25

19 Jan '25

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85864?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl{2...4}: Simplify SD code as well as for mc_ehl5 ...................................................................... mb/siemens/mc_ehl{2...4}: Simplify SD code as well as for mc_ehl5 The latest patch chain for mc_ehl5, commit 2d9a82cf8a57 ("mb/siemens/mc_ehl5: Rename SDIO converge layer register defines") and following patches, have simplified the SD card code. This patch now adapts the other mc_ehl mainboards accordingly to standardize the code. Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85864 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c 3 files changed, 56 insertions(+), 51 deletions(-) Approvals: Uwe Poeche: Looks good to me, but someone else must approve build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index 1121399..dd90d6f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -10,12 +10,21 @@ #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 -#define SD_CAP_BYP_SDR50 (1 << 13) -#define SD_CAP_BYP_SDR104 (1 << 14) -#define SD_CAP_BYP_DDR50 (1 << 15) +#define MMC_CAP_BYP 0x810 +#define MMC_CAP_BYP_EN 0x5A +#define MMC_CAP_BYP_REG1 0x814 +#define MMC_CAP_BYP_SDR50 (1 << 13) +#define MMC_CAP_BYP_SDR104 (1 << 14) +#define MMC_CAP_BYP_DDR50 (1 << 15) + +/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ +static void disable_sdr_modes(struct resource *res) +{ + write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN); + clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0), + MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50, + MMC_CAP_BYP_DDR50); +} void variant_mainboard_final(void) { @@ -30,26 +39,16 @@ if (dev) pci_write_config8(dev, 0xd8, 0x3e); - /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to - layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { - uint32_t reg; - uint16_t reg16; struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); - /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ - reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); - reg |= SD_CAP_BYP_DDR50; - write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + + disable_sdr_modes(res); /* Use preset driver strength from preset value registers. */ - reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); - reg16 |= HOSTCTRL2_PRESET; - write16(res2mmio(res, HOSTCTRL2, 0), reg16); + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c index ca52e7b..d76ac03 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c @@ -2,43 +2,44 @@ #include <baseboard/variants.h> #include <bootstate.h> -#include <device/mmio.h> +#include <device/pci_ids.h> #include <gpio.h> +#include <intelblocks/pcr.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 -#define SD_CAP_BYP_SDR50 (1 << 13) -#define SD_CAP_BYP_SDR104 (1 << 14) -#define SD_CAP_BYP_DDR50 (1 << 15) +#define MMC_CAP_BYP 0x810 +#define MMC_CAP_BYP_EN 0x5A +#define MMC_CAP_BYP_REG1 0x814 +#define MMC_CAP_BYP_SDR50 (1 << 13) +#define MMC_CAP_BYP_SDR104 (1 << 14) +#define MMC_CAP_BYP_DDR50 (1 << 15) + +/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ +static void disable_sdr_modes(struct resource *res) +{ + write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN); + clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0), + MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50, + MMC_CAP_BYP_DDR50); +} void variant_mainboard_final(void) { struct device *dev; - /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to - layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { - uint32_t reg; - uint16_t reg16; struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); - /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ - reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); - reg |= SD_CAP_BYP_DDR50; - write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + + disable_sdr_modes(res); /* Use preset driver strength from preset value registers. */ - reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); - reg16 |= HOSTCTRL2_PRESET; - write16(res2mmio(res, HOSTCTRL2, 0), reg16); + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c index 8accade..3ef72fd 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c @@ -9,28 +9,33 @@ #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 -#define SD_CAP_BYP_SDR50 (1 << 13) -#define SD_CAP_BYP_SDR104 (1 << 14) -#define SD_CAP_BYP_DDR50 (1 << 15) +#define MMC_CAP_BYP 0x810 +#define MMC_CAP_BYP_EN 0x5A +#define MMC_CAP_BYP_REG1 0x814 +#define MMC_CAP_BYP_SDR50 (1 << 13) +#define MMC_CAP_BYP_SDR104 (1 << 14) +#define MMC_CAP_BYP_DDR50 (1 << 15) + +/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ +static void disable_sdr_modes(struct resource *res) +{ + write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN); + clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0), + MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50, + MMC_CAP_BYP_DDR50); +} void variant_mainboard_final(void) { struct device *dev; - /* Limit SD card speed to DDR50 mode to avoid SDR104/SDR50 modes due to - layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - clrsetbits32(res2mmio(res, SD_CAP_BYP_REG1, 0), - SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50, - SD_CAP_BYP_DDR50); + + disable_sdr_modes(res); /* Use preset driver strength from preset value registers. */ clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); -- To view, visit https://review.coreboot.org/c/coreboot/+/85864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Gerrit-Change-Number: 85864 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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