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Hello Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85974?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins)
Change subject: mb/starlabs/starlite_adl: Select more appropriate macros for USB ports
......................................................................
mb/starlabs/starlite_adl: Select more appropriate macros for USB ports
Add the trace lengths as comments, and update the macros used for the
USB ports accordingly.
Like other boards, avoid the `USB2_PORT_TYPE_C` macro, as it makes
ports behave inconsistantly.
Change-Id: Id193b3ed86c58aedc7d5a1f384f2829a2bf18671
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85974/5
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Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email )
Change subject: soc/amd/glinda/cpu: Update cache info
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85640/comment/b43d9073_b8360246?us… :
PS3, Line 8:
> Please add that to the commit message.
Sure. Will do that in next patchset
File src/soc/amd/glinda/cpu.c:
https://review.coreboot.org/c/coreboot/+/85640/comment/2adeed4a_4f152b2d?us… :
PS3, Line 43: fill_cpu_cache_info
> For level=(0-2) it's identical to `fill_cpu_cache_info`. […]
I guess you imply that:
Use fill_cpu_cache_info which intern can call SoC specific handler(say soc_fill_cpu_cache_info) which if returns valid data then use it else fallback to previous implementation?
If so then yes I can update it in that way.
Also with the cpu_cache_info in heap, zen_2_3_init can update it & can be update the information in soc_fill_cpu_cache_info for level 3.
Let me know your thought & suggestion/improvements on that.
Thanks
https://review.coreboot.org/c/coreboot/+/85640/comment/2c0c8456_71fe8b85?us… :
PS3, Line 60: struct cpu_cache_info info_list
> Can you move `struct cpu_cache_info` to the heap and fill it in `zen_2_3_init` for LVL3 only?
Yes.
https://review.coreboot.org/c/coreboot/+/85640/comment/326e67a3_39ae0f0b?us… :
PS3, Line 66: memcpy(info, &info_list[0], sizeof(*info));
> Oh, wait. This is only copying one element of the array. […]
Acknowledged
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Change subject: util/crossgcc: Update variable use
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85718/comment/9ed5283c_6eb2b5cf?us… :
PS2, Line 7: Update variable use
Maybe be more specific:
> Quote DESTDIR to prevent unintended separation and globbing
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Change subject: mb/google/rauru: Add DVFS support in romstage
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/rauru/romstage.c:
https://review.coreboot.org/c/coreboot/+/86042/comment/968a2354_52448991?us… :
PS4, Line 46: dvfs_init();
> Ah, you're correct.
Thanks~ 😊
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Change subject: mb/google/rauru: Add DVFS support in romstage
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Patch Set 4: Code-Review+2
(1 comment)
File src/mainboard/google/rauru/romstage.c:
https://review.coreboot.org/c/coreboot/+/86042/comment/7e150013_dc22e3c2?us… :
PS4, Line 46: dvfs_init();
> Hi Yu-ping, this is romstage. kraken will run during the ramstage (soc.c). […]
Ah, you're correct.
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Change subject: mb/google/rauru: Add DVFS support in romstage
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/rauru/romstage.c:
https://review.coreboot.org/c/coreboot/+/86042/comment/bbe1bf16_2a739ed1?us… :
PS4, Line 46: dvfs_init();
> Then, shouldn't we move `dvfs_init` call somewhere before `mtk_fsp_load_and_run`?
Hi Yu-ping, this is romstage. kraken will run during the ramstage (soc.c).
As far as I know, soc.c should execute after romstage.c. Or did I misunderstand your point? thanks
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Change subject: mb/google/rauru: Add panel driver in mainboard
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Patch Set 9: Code-Review+2
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Change subject: mb/google/rauru: Add DVFS support in romstage
......................................................................
Patch Set 4: -Code-Review
(1 comment)
File src/mainboard/google/rauru/romstage.c:
https://review.coreboot.org/c/coreboot/+/86042/comment/aeb145bf_55f4f6c7?us… :
PS4, Line 46: dvfs_init();
> Hi Yu-ping, […]
Then, shouldn't we move `dvfs_init` call somewhere before `mtk_fsp_load_and_run`?
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Change subject: mb/google/fatcat: Enable SAGv
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Patch Set 2: Code-Review+2
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