coreboot-gerrit January 2025

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[M] Change in coreboot[main]: mb/google/rauru: Add panel driver in mainboard
by Bincai Liu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Bincai Liu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85951?usp=email ) Change subject: mb/google/rauru: Add panel driver in mainboard ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85951/comment/4061e70a_f96890b2?us… : PS2, Line 7: mb/google/rauru: Add edp driver in mainboard : : Add edp driver : Adjust training flow and turn off phy power beforce phy : configurate because maby link training fail > I think Yidi was asking to modify the commit message Done File src/mainboard/google/rauru/panel_navi.c: PS2: > Here is different, where the Navi function is called when FW config is oled. […] Done https://review.coreboot.org/c/coreboot/+/85951/comment/5a64a482_36cf3441?us… : PS2, Line 15: struct panel_description *get_navi_description(void); > Yes, create a new header. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Gerrit-Change-Number: 85951 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 08:30:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Bincai Liu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Jitao Shi, Yidi Lin, Yu-Ping Wu. Bincai Liu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 7: (53 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85949/comment/4670aca5_32ca8ec4?us… : PS2, Line 10: traning > Do you mean `training`? Done https://review.coreboot.org/c/coreboot/+/85949/comment/421d0045_786cb290?us… : PS2, Line 11: > Please mention what DVO is in the commit message. Done File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/9a8acc99_8345f613?us… : PS2, Line 91: 0x20 > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/5495a009_d8ee3b5c?us… : PS2, Line 99: gs_level > not done Done https://review.coreboot.org/c/coreboot/+/85949/comment/9bb8fa2f_05fc7b1b?us… : PS2, Line 162: 0x8000 > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/691811f4_2bce5fd2?us… : PS2, Line 198: mtk_dvo_power_on > will fix next patchset Done File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/20c9b6a9_31cd56a2?us… : PS4, Line 102: mtk_dvo_gs[MTK_DVO_8K_30FPS] > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/011686ef_aa3a49cf?us… : PS4, Line 106: 0xFFFFFFF > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/ad3f7693_accb1357?us… : PS4, Line 108: 0xFFFFFFF > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/a7664251_06648169?us… : PS4, Line 133: [dvo] > will fix next patchset Done File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/6911dfe6_5e0879d4?us… : PS6, Line 32: const struct mtk_dvo_sync_param *sync) > will fix next patchset Done File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/7a6613a4_2b0f2734?us… : PS2, Line 257: mtk_dp->train_info.linkrate = (linkrate >= mtk_dp->train_info.sys_max_linkrate) ? > Not done. […] Done https://review.coreboot.org/c/coreboot/+/85949/comment/fead9273_600f082e?us… : PS2, Line 372: write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR0, 0xFFFFFFFF); : write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR1, 0x00040000); > this clock is already configured in mainboard.c,we will remove in dptx.c and mtk_dpintf.c […] Done File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/5d11c5dc_cc552576?us… : PS4, Line 41: case DPTX_PATTERN_UNKNOWN: : printk(BIOS_ERR, "Pattern unknown\n"); : mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, 0x0, PATTERN_EN_DP_TRANS_4P_MASK); : return; : default: : mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, 0x0, PATTERN_EN_DP_TRANS_4P_MASK); : return; > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/af24de55_c8a1452f?us… : PS4, Line 54: u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE]) > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/9e1415a8_564f1855?us… : PS4, Line 92: lanerate > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/c97a03bd_64e1767a?us… : PS4, Line 94: lane_count > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/ba34ee2b_bbde2934?us… : PS4, Line 96: u8 target_link_rate = lanerate; : u8 target_lane_count = lanecount; > will fix next patchset Acknowledged https://review.coreboot.org/c/coreboot/+/85949/comment/ea2b191e_616bc0ce?us… : PS4, Line 140: DPTX_PLUG_OUT > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/ed9a9582_34938ea7?us… : PS4, Line 385: add 26Mhz > `Add 26MHz` Done https://review.coreboot.org/c/coreboot/+/85949/comment/ca8f6182_135d4f20?us… : PS4, Line 406: " > will fix next patchset Done File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/c8a08199_d9a7fd7f?us… : PS6, Line 260: 0x1f > 0x1F Done https://review.coreboot.org/c/coreboot/+/85949/comment/2b64d3d0_23930aaa?us… : PS6, Line 272: 0xbf > 0xBF Done https://review.coreboot.org/c/coreboot/+/85949/comment/d1099b3f_cceb3024?us… : PS6, Line 376: int mtk_edp_init(struct mtk_dp *mtk_dp,struct edid *edid) > > `space required after that ',' (ctx:VxV)` […] Done https://review.coreboot.org/c/coreboot/+/85949/comment/ebd69974_49faa28c?us… : PS6, Line 384: mdelay > udelay(50) is ok. […] Done File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/04faf19f_5304631b?us… : PS2, Line 52: switch (out_format) { > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/9ca86294_7609c030?us… : PS2, Line 146: switch (value) { > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/5724fd3a_1236ee68?us… : PS2, Line 307: mtk_edp_hal_reset_swing_pre_emphasis > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/58cd074f_1d9a4f10?us… : PS2, Line 369: if ((value << 2) <= UINT8_MAX) { > assert not added yet Done File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/b143d30a_69b8f446?us… : PS4, Line 39: 0xA << 2 > That's even better. Done https://review.coreboot.org/c/coreboot/+/85949/comment/a4c7f97c_fa43f142?us… : PS4, Line 53: switch (out_format) { > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/6e5205f1_fa5b1fba?us… : PS4, Line 86: u8 *swing_val, u8 *pre_emphasis) > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/aec9700b_9c121a8c?us… : PS4, Line 135: GENMASK(2, 0)); > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/f64aff26_d51cdc4e?us… : PS4, Line 142: switch (value) { > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/78b2a6d2_3294f2d4?us… : PS4, Line 337: (mtk_dp_phy_read > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/ade5a676_e7d5f9f6?us… : PS4, Line 337: 0x146c > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/9b579e7e_352b125c?us… : PS4, Line 362: mtk_dp_set_swing_pre_emphasis > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/885da47b_96137066?us… : PS4, Line 362: pre_emphasis > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/21e0b0eb_a30caf48?us… : PS4, Line 363: pre_emphasis > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/7b780d3f_2517eb07?us… : PS4, Line 388: , > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/7a8e0a0a_1b602eb6?us… : PS4, Line 389: break > will fix next patchset Done File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/26c346aa_cbde3352?us… : PS6, Line 316: mdelay > will fix next Patchset, […] Done https://review.coreboot.org/c/coreboot/+/85949/comment/9fb0e096_2f261de3?us… : PS6, Line 338: mdelay > Here is polling PHY ready, […] Done File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/8bf2daa7_0fd3d457?us… : PS6, Line 137: 0x6c > will fix next patchset Done https://review.coreboot.org/c/coreboot/+/85949/comment/0c44d811_61036826?us… : PS6, Line 141: c > will fix next patchset Done File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/ffb38afb_ff1f418b?us… : PS4, Line 112: #define HACT_SHIFT 16 > align Done https://review.coreboot.org/c/coreboot/+/85949/comment/ead88df1_715f9ac9?us… : PS4, Line 124: #define VACT_SHIFT 16 > will fix next patchset Done File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/93ce2e7f_83b03202?us… : PS2, Line 199: gs_level > will be used in mt8196/dp_intf. […] Done File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/26ff98b4_e89f4ecc?us… : PS4, Line 26: pre_emphasis > will be fix next patch Done https://review.coreboot.org/c/coreboot/+/85949/comment/44167963_8a8cb48d?us… : PS4, Line 31: pre_emphasis > will be fix next patch. Done https://review.coreboot.org/c/coreboot/+/85949/comment/58ddf07b_b50bf28f?us… : PS4, Line 32: pre_emphasis > will be fix next patch Done File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/824e5b2e_05613794?us… : PS2, Line 38: void mtk_edp_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp); : void mtk_edp_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable); : void mtk_edp_set_swing_pre_emphasis > will be change to dptx_hal_ next patchset Done File src/soc/mediatek/mt8196/include/soc/dptx_reg.h: https://review.coreboot.org/c/coreboot/+/85949/comment/ee962bab_07035eb0?us… : PS4, Line 204: #define DP_TRAIN_VOLTAGE_PREEMPHASIS_LEVEL_3 0x3 > will fix next patchset Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 08:29:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: mb/google/brya: Create moxie variant
by David Wu (Code Review) 20 Jan '25

20 Jan '25

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86061?usp=email ) Change subject: mb/google/brya: Create moxie variant ...................................................................... mb/google/brya: Create moxie variant Create the moxie variant of the kuldax project by copying the files to a new directory named for the variant. BUG=b:389391652 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MOXIE Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/moxie/Makefile.mk A src/mainboard/google/brya/variants/moxie/data.vbt A src/mainboard/google/brya/variants/moxie/fw_config.c A src/mainboard/google/brya/variants/moxie/gpio.c A src/mainboard/google/brya/variants/moxie/include/variant/ec.h A src/mainboard/google/brya/variants/moxie/include/variant/gpio.h A src/mainboard/google/brya/variants/moxie/overridetree.cb A src/mainboard/google/brya/variants/moxie/ramstage.c A src/mainboard/google/brya/variants/moxie/variant.c 11 files changed, 676 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/86061/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e4f563e..46f4cf9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -352,6 +352,14 @@ select BOARD_GOOGLE_BASEBOARD_BRASK select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_MOXIE + select BOARD_GOOGLE_BASEBOARD_BRASK + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9755 + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_RAPTORLAKE + config BOARD_GOOGLE_NIVVIKS select BOARD_GOOGLE_BASEBOARD_NISSA select BOARD_ROMSIZE_KB_32768 @@ -756,6 +764,7 @@ default 0x1 if BOARD_GOOGLE_MARASOV default 0x1 if BOARD_GOOGLE_MITHRAX default 0x1 if BOARD_GOOGLE_MOLI + default 0x1 if BOARD_GOOGLE_MOXIE default 0x0 if BOARD_GOOGLE_NEREID default 0x0 if BOARD_GOOGLE_NIVVIKS default 0x1 if BOARD_GOOGLE_NOVA @@ -835,6 +844,7 @@ default 13 if BOARD_GOOGLE_MARASOV default 13 if BOARD_GOOGLE_MITHRAX default 13 if BOARD_GOOGLE_MOLI + default 13 if BOARD_GOOGLE_MOXIE default 13 if BOARD_GOOGLE_NEREID default 13 if BOARD_GOOGLE_NIVVIKS default 13 if BOARD_GOOGLE_NOVA @@ -918,6 +928,7 @@ default "Marasov" if BOARD_GOOGLE_MARASOV default "Mithrax" if BOARD_GOOGLE_MITHRAX default "Moli" if BOARD_GOOGLE_MOLI + default "Moxie" if BOARD_GOOGLE_MOXIE default "Nereid" if BOARD_GOOGLE_NEREID default "Nivviks" if BOARD_GOOGLE_NIVVIKS default "Nokris" if BOARD_GOOGLE_NOKRIS @@ -990,6 +1001,7 @@ default "marasov" if BOARD_GOOGLE_MARASOV default "mithrax" if BOARD_GOOGLE_MITHRAX default "moli" if BOARD_GOOGLE_MOLI + default "moxie" if BOARD_GOOGLE_MOXIE default "nereid" if BOARD_GOOGLE_NEREID default "nereid" if BOARD_GOOGLE_TEREID default "nivviks" if BOARD_GOOGLE_NIVVIKS diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7dd82d0..ca859a2 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -92,6 +92,9 @@ config BOARD_GOOGLE_MOLI bool "-> Moli" +config BOARD_GOOGLE_MOXIE + bool "-> Moxie" + config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" diff --git a/src/mainboard/google/brya/variants/moxie/Makefile.mk b/src/mainboard/google/brya/variants/moxie/Makefile.mk new file mode 100644 index 0000000..e31aaa1 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/Makefile.mk @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/moxie/data.vbt b/src/mainboard/google/brya/variants/moxie/data.vbt new file mode 100644 index 0000000..7d14588 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/moxie/fw_config.c b/src/mainboard/google/brya/variants/moxie/fw_config.c new file mode 100644 index 0000000..42613af --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/fw_config.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } else { + printk(BIOS_INFO, "BT offload disabled\n"); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/moxie/gpio.c b/src/mainboard/google/brya/variants/moxie/gpio.c new file mode 100644 index 0000000..556e8b6 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/gpio.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* C3 : SML0CLK ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6), + /* C4 : SML0DATA ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + + /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/moxie/include/variant/ec.h b/src/mainboard/google/brya/variants/moxie/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h b/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/moxie/overridetree.cb b/src/mainboard/google/brya/variants/moxie/overridetree.cb new file mode 100644 index 0000000..19a20a1 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/overridetree.cb @@ -0,0 +1,347 @@ +fw_config + field AUDIO 0 2 + option AUDIO_UNKNOWN 0 + option NAU88L25B_I2S 1 + end + field BJ_POWER 3 4 + option BJ_POWER_150W 0 + option BJ_POWER_230W 1 + option BJ_POWER_65W 2 + option BJ_POWER_135W 3 + end + field MB_USBC 6 7 + option TC_USB4 0 + option TC_USB3 1 + end + field USB_HUB 32 + option HUB_ABSENT 0 + option HUB_PRESENT 1 + end +end + +chip soc/intel/alderlake + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .enable_fast_vmode = 1, + }" + + register "sagv" = "SaGv_Enabled" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A0 + register "usb3_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A1 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 100, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp0 on + probe MB_USBC TC_USB4 + end + device ref tbt_pcie_rp1 on + probe MB_USBC TC_USB4 + end + device ref tbt_pcie_rp2 on + probe MB_USBC TC_USB4 + end + device ref tcss_dma0 on + probe MB_USBC TC_USB4 + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_pull_up" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0C" + register "sar_threshold[1]" = "0x1C" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on + probe AUDIO NAU88L25B_I2S + end + end + end + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_leds" = "0x05af" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8125 and RTL8111K Ethernet NIC + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on + probe USB_HUB HUB_ABSENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port9 on + probe USB_HUB HUB_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on + probe USB_HUB HUB_ABSENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port1 on + probe USB_HUB HUB_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/moxie/ramstage.c b/src/mainboard/google/brya/variants/moxie/ramstage.c new file mode 100644 index 0000000..f4f80be --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/ramstage.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_RPL_P_ID_5, 15, 138 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 138 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 138 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in moxie, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 11.25A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W + * For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W + * For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system + * power = 225W * 5A / 11.25A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 11250, + .bj_volts_mv = 20000 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brya/variants/moxie/variant.c b/src/mainboard/google/brya/variants/moxie/variant.c new file mode 100644 index 0000000..b7cba96 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + NAU88L25B_I2S)); + + if (fw_config_probe(FW_CONFIG(MB_USBC, TC_USB3))) { + config->tcss_aux_ori = 1; + config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_C3; + config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_C4; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86061?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712 Gerrit-Change-Number: 86061 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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[L] Change in coreboot[main]: [test]Upgrade GCC to 15-20250119 Snapshot
by Elyes Haouas (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Christian Walter, Elyes Haouas, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [test]Upgrade GCC to 15-20250119 Snapshot ...................................................................... [test]Upgrade GCC to 15-20250119 Snapshot Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 M payloads/external/Makefile.mk M payloads/libpayload/Makefile M payloads/libpayload/tests/Makefile.mk M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk M src/arch/riscv/fit_payload.c M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/include/bits.h M src/arch/riscv/include/mcall.h M src/arch/riscv/include/vm.h M src/arch/riscv/pmp.c M src/arch/riscv/ramstage.S M src/arch/riscv/sbi.c M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig.name M src/soc/ucb/riscv/Kconfig M tests/Makefile.common M util/cbfstool/Makefile.mk M util/cbfstool/lz4/lib/Makefile M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch R util/crossgcc/patches/gcc-15-20250119_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20250119_gnat.patch R util/crossgcc/patches/gcc-15-20250119_libcpp.patch R util/crossgcc/patches/gcc-15-20250119_libgcc.patch R util/crossgcc/patches/gcc-15-20250119_musl_poisoned_calloc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20250119.tar.xz.cksum M util/qemu/Makefile.mk M util/superiotool/Makefile 35 files changed, 73 insertions(+), 305 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 15 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Jarried Lin (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin. Hello Bincai Liu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85949?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... soc/mediatek/mt8196: Add eDP driver Add eDP driver to adjust training flow and turn off PHY power before PHY configuration to prevent potential link training failures. DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI or simply digital video output. DISP represents “display”, while DVO is the abbreviation of “digital video output”. This version of DISP_DVO is mainly designed for eDP1.5 protocol. TEST=check edp training pass and show log: EQ training pass BUG=b:343351631 Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/dp_intf.c A src/soc/mediatek/mt8196/dptx.c A src/soc/mediatek/mt8196/dptx_hal.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/dp_intf.h A src/soc/mediatek/mt8196/include/soc/dptx.h A src/soc/mediatek/mt8196/include/soc/dptx_hal.h A src/soc/mediatek/mt8196/include/soc/dptx_reg.h 10 files changed, 1,465 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85949/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add panel driver in mainboard
by Jarried Lin (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Bincai Liu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85951?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Add panel driver in mainboard ...................................................................... mb/google/rauru: Add panel driver in mainboard Add panel driver in mainboard for ruaru project and support oled eDP panel. TEST=check edp training pass and show log: EQ training pass BUG=b:343351631 Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/Makefile.mk M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h A src/mainboard/google/rauru/panel.c A src/mainboard/google/rauru/panel.h A src/mainboard/google/rauru/panel_oled.c 8 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85951/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Gerrit-Change-Number: 85951 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Zhaoqing Jiu. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86017/comment/a9f7fb6d_a883299d?us… : PS8, Line 11: TEST=Check temperatures read from each sensors. > Please paste the new log messages. Done Commit Message: https://review.coreboot.org/c/coreboot/+/86017/comment/bcb724c2_1b1dfd26?us… : PS9, Line 12: [0m Remove these control codes. -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:39:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Add DVFS support in romstage
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86042?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rauru: Add DVFS support in romstage ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rauru/romstage.c: https://review.coreboot.org/c/coreboot/+/86042/comment/e0c94f70_35d784cd?us… : PS4, Line 46: dvfs_init(); Just to confirm, this needs to run *after* the kraken driver (loading pi_img) in `mtk_fsp_load_and_run` above. Is that correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/86042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f290946365b4c5a650651ebea30ffc76583d2b2 Gerrit-Change-Number: 86042 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:36:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Add DVFS support in romstage
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86042?usp=email ) Change subject: mb/google/rauru: Add DVFS support in romstage ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f290946365b4c5a650651ebea30ffc76583d2b2 Gerrit-Change-Number: 86042 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:35:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add DVFS driver
by Yu-Ping Wu (Code Review) 19 Jan '25

19 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86041?usp=email ) Change subject: soc/mediatek/mt8196: Add DVFS driver ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2 Gerrit-Change-Number: 86041 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 07:35:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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