coreboot-gerrit January 2025

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Jarried Lin (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Bincai Liu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85949?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... soc/mediatek/mt8196: Add eDP driver Add eDP driver to adjust training flow and turn off PHY power before PHY configuration to prevent potential link training failures. DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI or simply digital video output. DISP represents “display”, while DVO is the abbreviation of “digital video output”. This version of DISP_DVO is mainly designed for eDP1.5 protocol. TEST=check edp training pass and show log: EQ training pass BUG=b:343351631 Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/dp_intf.c A src/soc/mediatek/mt8196/dptx.c A src/soc/mediatek/mt8196/dptx_hal.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/dp_intf.h A src/soc/mediatek/mt8196/include/soc/dptx.h A src/soc/mediatek/mt8196/include/soc/dptx_hal.h A src/soc/mediatek/mt8196/include/soc/dptx_reg.h 10 files changed, 1,452 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85949/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Jitao Shi (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin, Yidi Lin. Jitao Shi has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 8: (7 comments) File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/c3689508_745ca166?us… : PS7, Line 181: .regs_ck = (void *)CKSYS_GP2_BASE, : .regs_mm = (void *)MMSYS1_CONFIG_BASE, > Remove these two unused fields from here and the header. Done https://review.coreboot.org/c/coreboot/+/85949/comment/d20ff022_baf7a905?us… : PS7, Line 191: mtk_dpintf_power_on > Now this name becomes inconsistent with other function names in this file. […] Done File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/63f00c41_5dd6a9f4?us… : PS7, Line 269: linkrate = mtk_dp->train_info.linkrate; : lanecount = mtk_dp->train_info.linklane_count; > This is wrong. By the time we reach here, `mtk_dp->train_info.*` haven't been set yet. […] Done https://review.coreboot.org/c/coreboot/+/85949/comment/238e18a0_3dc0eba4?us… : PS7, Line 370: int mtk_edp_init(struct mtk_dp *mtk_dp,struct edid *edid) > > `space required after that ',' (ctx:VxV)` […] Done https://review.coreboot.org/c/coreboot/+/85949/comment/49570954_f02d54d9?us… : PS7, Line 374: 0xFF000000 > Please confirm if this is supposed to be 0xFF000000 or 0x80000000. Done https://review.coreboot.org/c/coreboot/+/85949/comment/bc00ea6c_46d1741f?us… : PS7, Line 376: m > u Done https://review.coreboot.org/c/coreboot/+/85949/comment/708b9eb9_3d9be482?us… : PS7, Line 393: %s > `%s: Failed to ... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct USB port configuration for cameras
by Sean Rhodes (Code Review) 20 Jan '25

20 Jan '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86064?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/starlabs/starlite_adl: Correct USB port configuration for cameras ...................................................................... mb/starlabs/starlite_adl: Correct USB port configuration for cameras Both cameras share the same USB 2.0 interface, rather than using their own port. Update the configuration to match this. Change-Id: Ia2d8698394de69af53489e3a08c7fe7b4f2fbc07 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/cfr.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 4 files changed, 4 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86064/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2d8698394de69af53489e3a08c7fe7b4f2fbc07 Gerrit-Change-Number: 86064 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add DVFS driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86041?usp=email ) Change subject: soc/mediatek/mt8196: Add DVFS driver ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86041/comment/5e653dbc_9668e07f?us… : PS2, Line 8: > Please elaborate. Update? -- To view, visit https://review.coreboot.org/c/coreboot/+/86041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2 Gerrit-Change-Number: 86041 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:41:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add DVFS driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86041?usp=email ) Change subject: soc/mediatek/mt8196: Add DVFS driver ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/include/soc/mtk_dvfs.h: https://review.coreboot.org/c/coreboot/+/86041/comment/1660295b_10b51b52?us… : PS2, Line 9: C > Hi Yuping, the "CSRAM" means "Chip SRAM". Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2 Gerrit-Change-Number: 86041 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:40:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin, Jitao Shi, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 8: Code-Review+2 (9 comments) File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/16c1aacc_6709aac9?us… : PS7, Line 95: 0x20 > `0x20 << EXT_TG_DLY_LINE` Done https://review.coreboot.org/c/coreboot/+/85949/comment/906dd603_30dc5819?us… : PS7, Line 100: if (dvo->gs_level >= MTK_DVO_GSL_MAX) : return; > `assert(dvo->gs_level < MTK_DVO_GSL_MAX)` Done File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/8a896ecc_a861a131?us… : PS7, Line 52: u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE]) > align Done https://review.coreboot.org/c/coreboot/+/85949/comment/0ebdff38_9f8dac3f?us… : PS7, Line 70: DP_TRAIN_VOLTAGE_SWING_LEVEL_3 > DPTX_SWING3 Done File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/339825de_9be18440?us… : PS7, Line 106: mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, 0x18); : mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, 0x6); > Can we merge these into a single call? […] Done https://review.coreboot.org/c/coreboot/+/85949/comment/717fae32_53fdd21f?us… : PS7, Line 290: dptx_hal_reset_swing_preemphasis_mt8196 > How about `dptx_hal_swing_emp_reset` (to be consistent with `dptx_hal_phyd_reset` below)? Done File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/0b4f97f3_5466f0cd?us… : PS8, Line 106: mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, EDP_TX_LN_VOLT_SWING_VAL_MASK | Move mask to the next line. File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/8bef6491_b65e494d?us… : PS7, Line 32: u8 *preemphasis); > align Done File src/soc/mediatek/mt8196/include/soc/dptx_reg.h: https://review.coreboot.org/c/coreboot/+/85949/comment/a8ed68ef_8666a54b?us… : PS7, Line 198: DP_TRAIN_VOLTAGE_SWING_LEVEL_3 > Also duplicate of `DPTX_SWING3`. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Johannes Hahn (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Mario Scheithauer, Uwe Poeche, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86068?usp=email ) Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86068/comment/bf978da7_8fc8ebd1?us… : PS1, Line 12: == 0 > I think you can leave that out. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 2 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:38:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Johannes Hahn (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Johannes Hahn, Uwe Poeche, Werner Zeh. Hello Intel coreboot Reviewers, Mario Scheithauer, Uwe Poeche, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86068?usp=email to look at the new patch set (#2). Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param According to Intel's recommendation for Time Coordinated Computing (TCC) the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled' in order to promote low latencies on the PCH. With the previous setting 'Disbaled' low latencies on the PCH for I/O operations are not enhanced. Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/soc/intel/elkhartlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/86068/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 2 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add DVFS driver
by Jarried Lin (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86041?usp=email ) Change subject: soc/mediatek/mt8196: Add DVFS driver ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/include/soc/mtk_dvfs.h: https://review.coreboot.org/c/coreboot/+/86041/comment/9aab3d41_5b137b25?us… : PS2, Line 9: C > What does "C" mean here? Hi Yuping, the "CSRAM" means "Chip SRAM". -- To view, visit https://review.coreboot.org/c/coreboot/+/86041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2 Gerrit-Change-Number: 86041 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:31:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Mario Scheithauer (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Johannes Hahn, Uwe Poeche, Werner Zeh. Mario Scheithauer has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86068?usp=email ) Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86068/comment/d03acc07_188123aa?us… : PS1, Line 7: soc/intel/elkhartlake/fsp_params.c: soc/intel/ehl/fsp_params: makes it a bit shorter, but it's up to you https://review.coreboot.org/c/coreboot/+/86068/comment/85a8a051_035970b9?us… : PS1, Line 12: == 0 I think you can leave that out. -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 1 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 13:26:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025