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Change subject: mb/google/rauru: Configure firmware display for eDP panel
......................................................................
Patch Set 13: Code-Review+2
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Change subject: mb/google/rauru: Add panel driver in mainboard
......................................................................
Patch Set 11:
(2 comments)
File src/mainboard/google/rauru/panel_oled.c:
https://review.coreboot.org/c/coreboot/+/85951/comment/d69720f6_b65ce11a?us… :
PS11, Line 19: mdelay(400);
I don't think we need this. We take more than 400ms before jumping to payload. (eDP already takes 200ms)
https://review.coreboot.org/c/coreboot/+/85951/comment/989d7340_00a8df6a?us… :
PS11, Line 20: gpio_output(GPIO_AP_EDP_BKLTEN, 1);
: gpio_output(GPIO_BL_PWM_1V8, 1);
We turn on the backlight in the payload. So we should turn off them here.
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Change subject: soc/mediatek/mt8196: Add eDP driver
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Patch Set 9: Code-Review+2
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Change subject: mb/google/rauru: Add DVFS support in romstage
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add DVFS driver
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Patch Set 4: Code-Review+2
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Change subject: soc/mediatek/mt8196: Fix issue with incomplete modem disable
......................................................................
Patch Set 1: Code-Review+2
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85844?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review+1 by Kun Liu, Verified+1 by build bot (Jenkins)
Change subject: mb/google/brya: Create pujjoniru variant
......................................................................
mb/google/brya: Create pujjoniru variant
Create the pujjoniru variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics PujjoNiru_C5_CHROME_TWL_SCH_MB_V1_1225A.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:386221423
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJONIRU
Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0
Signed-off-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/pujjoniru/Makefile.mk
A src/mainboard/google/brya/variants/pujjoniru/gpio.c
A src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h
A src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
A src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk
A src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
A src/mainboard/google/brya/variants/pujjoniru/variant.c
11 files changed, 900 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85844/9
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Hello build bot (Jenkins),
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Change subject: mb/starlabs/starlite_adl: Enable TLS Confidentiality GPIO
......................................................................
mb/starlabs/starlite_adl: Enable TLS Confidentiality GPIO
This board does not have a 20K Pull Down resistor fitted here,
meaning this will not change anything. However, it unifies the
the configuration with the other Star Labs boards.
Change-Id: Iee0adea21c124e0a421a1506310944cc883a73fb
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/86066/2
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Change subject: mb/starlabs/starlite_adl: Disconnect unused GPIOs
......................................................................
Patch Set 1: Code-Review+2
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