coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dvfs driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86041?usp=email ) Change subject: soc/mediatek/mt8196: Add dvfs driver ...................................................................... Patch Set 2: (9 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/86041/comment/23d620e9_a0acd280?us… : PS2, Line 7: dvfs DVFS https://review.coreboot.org/c/coreboot/+/86041/comment/2c2db27e_5d8eb354?us… : PS2, Line 8: Please elaborate. File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/86041/comment/03ed6bfa_c8b7529d?us… : PS2, Line 43: romstage-y += mtk_dvfs.c Rename and sort this. https://review.coreboot.org/c/coreboot/+/86041/comment/8e21d48f_9c645b4e?us… : PS2, Line 45: mtk_pwrsel Note that I also renamed this in CB:86059. File src/soc/mediatek/mt8196/include/soc/mtk_dvfs.h: PS2: Rename to dvfs.h https://review.coreboot.org/c/coreboot/+/86041/comment/4c661fb3_a146b934?us… : PS2, Line 3: MTK_DVFS DVFS https://review.coreboot.org/c/coreboot/+/86041/comment/27083946_972db8d6?us… : PS2, Line 9: C What does "C" mean here? File src/soc/mediatek/mt8196/mtk_dvfs.c: PS2: Rename dvfs.c https://review.coreboot.org/c/coreboot/+/86041/comment/a6ca7522_4c6d37e4?us… : PS2, Line 11: 0x01 `BIT(0)` -- To view, visit https://review.coreboot.org/c/coreboot/+/86041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2 Gerrit-Change-Number: 86041 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 02:37:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Rename mtk_pwrsel.* to pwrsel.*
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86059?usp=email ) Change subject: soc/mediatek/mt8196: Rename mtk_pwrsel.* to pwrsel.* ...................................................................... soc/mediatek/mt8196: Rename mtk_pwrsel.* to pwrsel.* As the mtk_pwrsel.{c,h} files are already under the soc/mediatek directory, drop the file name prefix "mtk_" from them. BUG=b:317009620 TEST=none Change-Id: I28131d44067c33b5d8682a85cc8a73fc42604de3 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk R src/soc/mediatek/mt8196/include/soc/pwrsel.h R src/soc/mediatek/mt8196/pwrsel.c 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86059/1 diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 32c8a61..7677995 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -10,10 +10,10 @@ #include <soc/mt6373.h> #include <soc/mt6685.h> #include <soc/mtk_fsp.h> -#include <soc/mtk_pwrsel.h> #include <soc/pcie.h> #include <soc/pll.h> #include <soc/pmif.h> +#include <soc/pwrsel.h> #include <soc/srclken_rc.h> static void raise_little_cpu_freq(void) diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 0ef442f..c12d7b0 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -41,7 +41,7 @@ romstage-y += ../common/mt6373.c mt6373.c romstage-y += ../common/mt6685.c mt6685.c romstage-y += ../common/mtk_fsp.c -romstage-y += mtk_pwrsel.c +romstage-y += pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c diff --git a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h b/src/soc/mediatek/mt8196/include/soc/pwrsel.h similarity index 74% rename from src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h rename to src/soc/mediatek/mt8196/include/soc/pwrsel.h index 327735e..7928ff9 100644 --- a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h +++ b/src/soc/mediatek/mt8196/include/soc/pwrsel.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#ifndef __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ -#define __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ +#ifndef __SOC_MEDIATEK_MT8196_PWRSEL__ +#define __SOC_MEDIATEK_MT8196_PWRSEL__ #include <soc/addressmap.h> @@ -15,4 +15,4 @@ void pwrsel_init(void); -#endif /* end of __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ */ +#endif /* end of __SOC_MEDIATEK_MT8196_PWRSEL__ */ diff --git a/src/soc/mediatek/mt8196/mtk_pwrsel.c b/src/soc/mediatek/mt8196/pwrsel.c similarity index 100% rename from src/soc/mediatek/mt8196/mtk_pwrsel.c rename to src/soc/mediatek/mt8196/pwrsel.c -- To view, visit https://review.coreboot.org/c/coreboot/+/86059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28131d44067c33b5d8682a85cc8a73fc42604de3 Gerrit-Change-Number: 86059 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add unmask eint event for bootblock
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: Add unmask eint event for bootblock ...................................................................... soc/mediatek/mt8196: Add unmask eint event for bootblock EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue "Can't wake using power button (cros_ec) or touchpad". So we add a driver here to unmask all wakeup sources. TEST=write eint data successfully. BUG=b:317009620 Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Signed-off-by: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84025 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/eint_event_info.c 3 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 80dac20..0ef442f 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -15,6 +15,7 @@ bootblock-y += ../common/bootblock.c bootblock.c bootblock-y += cksys.c bootblock-y += ../common/early_init.c +bootblock-y += ../common/eint_event.c eint_event_info.c bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += mminfra.c bootblock-y += ../common/mmu_operations.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index bd3c418..891a195 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -4,6 +4,7 @@ #include <bootblock_common.h> #include <soc/cksys.h> #include <soc/early_init.h> +#include <soc/eint_event.h> #include <soc/lastbus_v2.h> #include <soc/mminfra.h> #include <soc/mmu_operations.h> @@ -26,4 +27,5 @@ mt_pll_post_init(); mtcmos_post_init(); early_init_clear(); + unmask_eint_event_mask(); } diff --git a/src/soc/mediatek/mt8196/eint_event_info.c b/src/soc/mediatek/mt8196/eint_event_info.c new file mode 100644 index 0000000..5917b76 --- /dev/null +++ b/src/soc/mediatek/mt8196/eint_event_info.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/addressmap.h> +#include <soc/eint_event.h> + +const struct eint_event_info eint_event[] = { + {EINT_E_BASE, 75}, + {EINT_S_BASE, 29}, + {EINT_W_BASE, 58}, + {EINT_N_BASE, 47}, + {EINT_C_BASE, 25}, + {}, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 19 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 8: -Code-Review (4 comments) File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86017/comment/339c1b36_2dbe623d?us… : PS8, Line 38: */ > To avoid duplication, the comment should just be in one file? Please remove the duplicate comments in thermal_internal.h. https://review.coreboot.org/c/coreboot/+/86017/comment/66ae941f_f2c7b6e7?us… : PS8, Line 163: printk(BIOS_INFO, "%s: msr_raw=%u, temp_mc=%d\n", __func__, msr_raw, temp_mc); > Should be a debug message, or rewritten? Please change to `BIOS_DEBUG` https://review.coreboot.org/c/coreboot/+/86017/comment/1ca3aa62_ce7c38e7?us… : PS8, Line 170: uint32_t i; > size_t? I'd prefer using `int` for array index. `size_t` is for representing the size of a C object. Either way, `i`, `j`, `s_index` should all be changed to a native type. https://review.coreboot.org/c/coreboot/+/86017/comment/e1bcf8c4_c3778267?us… : PS8, Line 271: printk(BIOS_INFO, "%s\n", __func__); > Looks like a debug message. Can we remove this log? -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 02:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/*: Remove old USB configs from SNB/bd82x6x boards, part 2
by Elyes Haouas (Code Review) 20 Jan '25

20 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85942?usp=email ) Change subject: mb/*: Remove old USB configs from SNB/bd82x6x boards, part 2 ...................................................................... mb/*: Remove old USB configs from SNB/bd82x6x boards, part 2 As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. These stuff should have been removed then. Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85942 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c M src/mainboard/lenovo/t520/early_init.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/msi/ms7707/early_init.c M src/mainboard/supermicro/x9sae/early_init.c M src/mainboard/supermicro/x9scl/early_init.c 7 files changed, 0 insertions(+), 125 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Nicholas Chin: Looks good to me, approved diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index 8980572..b69c71d 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -4,27 +4,9 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/pmh7/pmh7.h> #include <types.h> -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, /* P0:, OC 0 */ - { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ - { 1, 1, 3 }, /* P2: OC 3 */ - { 1, 0, -1 }, /* P3: no OC */ - { 1, 2, -1 }, /* P4: no OC */ - { 1, 1, -1 }, /* P5: no OC */ - { 1, 1, -1 }, /* P6: no OC */ - { 0, 1, -1 }, /* P7: empty, no OC */ - { 1, 1, -1 }, /* P8: smart card reader, no OC */ - { 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 0, 0, -1 }, /* P12: wlan, no OC */ - { 1, 1, -1 }, /* P13: camera, no OC */ -}; - void mainboard_early_init(int s3resume) { u8 enable_peg = get_uint_option("enable_dual_graphics", 0); diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 6fbbaad..9a78bac 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,24 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, /* SSP1: right */ - { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ - { 1, 1, 3 }, /* SSP3: dock USB3 */ - { 1, 1, -1 }, /* B0P4: wwan USB */ - { 1, 1, 2 }, /* B0P5: dock USB2 */ - { 0, 0, -1 }, /* B0P6 */ - { 0, 0, -1 }, /* B0P7 */ - { 1, 2, -1 }, /* B0P8: unknown */ - { 1, 0, -1 }, /* B1P1: smart card reader */ - { 0, 2, 5 }, /* B1P2 */ - { 1, 1, -1 }, /* B1P3: fingerprint reader */ - { 0, 0, -1 }, /* B1P4 */ - { 1, 1, -1 }, /* B1P5: wlan USB */ - { 1, 1, -1 }, /* B1P6: Camera */ -}; void mb_get_spd_map(struct spd_info *spdi) { diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index 219ffc1..0b0a576 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -34,23 +34,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ - { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ - { 1, 2, -1 }, /* P2: wimax / WLAN */ - { 1, 1, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 2, -1 }, /* P6: empty */ - { 0, 2, -1 }, /* P7: to touch panel, no OC */ - { 1, 1, 4 }, /* P8: left dual conn, OC4 */ - { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */ - { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 2, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index b525a0b..bb24a26 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -2,27 +2,8 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled, current, OC pin */ - { 0, 3, 0 }, /* P00 disconnected */ - { 1, 1, 1 }, /* P01 left or right */ - { 0, 1, 3 }, /* P02 disconnected */ - { 1, 3, -1 },/* P03 WWAN */ - { 0, 1, 2 }, /* P04 disconnected */ - { 0, 1, -1 },/* P05 disconnected */ - { 0, 1, -1 },/* P06 disconnected */ - { 0, 2, -1 },/* P07 disconnected */ - { 0, 1, -1 },/* P08 disconnected */ - { 1, 2, 5 }, /* P09 left or right */ - { 1, 3, -1 },/* P10 FPR */ - { 1, 3, -1 },/* P11 Bluetooth */ - { 1, 1, -1 },/* P12 WLAN */ - { 1, 1, -1 },/* P13 Camera */ -}; - static unsigned int get_spd_index(void) { const int spd_gpio_vector[] = {25, 45, -1}; diff --git a/src/mainboard/msi/ms7707/early_init.c b/src/mainboard/msi/ms7707/early_init.c index 24ba8eb..ba0ad23 100644 --- a/src/mainboard/msi/ms7707/early_init.c +++ b/src/mainboard/msi/ms7707/early_init.c @@ -11,20 +11,3 @@ reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 0, 0}, - {1, 0, 0}, - {1, 0, 1}, - {1, 0, 1}, - {1, 0, 2}, - {1, 0, 2}, - {1, 0, 3}, - {1, 0, 3}, - {1, 0, 4}, - {1, 0, 4}, - {1, 0, 6}, - {1, 0, 5}, - {1, 0, 5}, - {1, 0, 6}, -}; diff --git a/src/mainboard/supermicro/x9sae/early_init.c b/src/mainboard/supermicro/x9sae/early_init.c index 5966b66..05d54e5 100644 --- a/src/mainboard/supermicro/x9sae/early_init.c +++ b/src/mainboard/supermicro/x9sae/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -10,23 +9,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index 2886666..c284240 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -5,7 +5,6 @@ #include <device/pnp_ops.h> #include <bootblock_common.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/wpcm450/wpcm450.h> @@ -18,23 +17,6 @@ #define SUPERIO_INITVAL(reg, data) {(reg), (data)} #define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x)) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ - { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ - { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ - { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ - { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ - { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ - { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ - { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ - { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ - { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ - { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ - { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - static const uint8_t superio_initvals[][2] = { /* Global config registers */ SUPERIO_INITVAL(0x1a, 0xc8), -- To view, visit https://review.coreboot.org/c/coreboot/+/85942?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79 Gerrit-Change-Number: 85942 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/find_usbdebug: Fix line indented with spaces instead of tabs
by Elyes Haouas (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Nicholas Chin. Elyes Haouas has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/86058?usp=email ) Change subject: util/find_usbdebug: Fix line indented with spaces instead of tabs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86058?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id131f68465330c183c7c6ba4c85cd098dfe9a94e Gerrit-Change-Number: 86058 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 01:12:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: docs/getting-started: Update guide for writing docs
by Elyes Haouas (Code Review) 20 Jan '25

20 Jan '25

Attention is currently required from: Nicholas Chin. Elyes Haouas has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85857?usp=email ) Change subject: docs/getting-started: Update guide for writing docs ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I569862e30fb88a421ad2338aafabeaf3ea76836a Gerrit-Change-Number: 85857 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 20 Jan 2025 01:11:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: [NOT FOR MERGE] Docs: Testing for CI
by Nicholas Chin (Code Review) 20 Jan '25

20 Jan '25

Nicholas Chin has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84884?usp=email ) Change subject: [NOT FOR MERGE] Docs: Testing for CI ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5bfab65462d63f4a22533613f9d9890c2698210d Gerrit-Change-Number: 84884 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer
by Nicholas Chin (Code Review) 20 Jan '25

20 Jan '25

Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85790?usp=email ) Change subject: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer ...................................................................... Patch Set 5: (1 comment) File util/find_usbdebug/find_usbdebug.sh: https://review.coreboot.org/c/coreboot/+/85790/comment/3aa51362_0969bbf2?us… : PS5, Line 50: > should be a tab instead of spaces Fixed in CB:86058 -- To view, visit https://review.coreboot.org/c/coreboot/+/85790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff Gerrit-Change-Number: 85790 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 20 Jan 2025 00:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: util/find_usbdebug: Fix line indented with spaces instead of tabs
by Nicholas Chin (Code Review) 20 Jan '25

20 Jan '25

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86058?usp=email ) Change subject: util/find_usbdebug: Fix line indented with spaces instead of tabs ...................................................................... util/find_usbdebug: Fix line indented with spaces instead of tabs Change-Id: Id131f68465330c183c7c6ba4c85cd098dfe9a94e Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/find_usbdebug/find_usbdebug.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/86058/1 diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh index 4606080..47d13a9 100755 --- a/util/find_usbdebug/find_usbdebug.sh +++ b/util/find_usbdebug/find_usbdebug.sh @@ -47,7 +47,7 @@ port=$2 # lsusb -t uses 3 digits for bus/port nunmbers as of version 016 and later - if [ $(lsusb -V | cut -f 3 -d " ") -lt 16 ]; then + if [ $(lsusb -V | cut -f 3 -d " ") -lt 16 ]; then busstr=`printf "Bus %02d" "$bus"` portstr="Port $port" else -- To view, visit https://review.coreboot.org/c/coreboot/+/86058?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id131f68465330c183c7c6ba4c85cd098dfe9a94e Gerrit-Change-Number: 86058 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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