coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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3913 discussions

[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Name of user not set (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Singer, Jérémy Compostella, Shuo Liu. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83320?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... soc/intel/common/block/imc: Add Integrated Memory Controller driver This patch wraps the smbus IO calls with spd IO functions so that firmware could use IMC to get SPD data. Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/include/spd_bin.h A src/soc/intel/common/block/imc/Kconfig A src/soc/intel/common/block/imc/Makefile.mk A src/soc/intel/common/block/imc/imc.c A src/soc/intel/common/block/imc/spd.c M src/soc/intel/common/block/include/intelblocks/imc.h M src/soc/intel/common/block/smbus/Makefile.mk M src/soc/intel/common/block/smbus/smbuslib.c A src/soc/intel/common/block/smbus/spd.c M src/southbridge/intel/common/smbus.c 10 files changed, 317 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/83320/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 14 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/ith.asl A src/soc/intel/snowridge/acpi/lpc.asl A src/soc/intel/snowridge/acpi/pch_irqs.asl A src/soc/intel/snowridge/acpi/pci_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/sata0.asl A src/soc/intel/snowridge/acpi/sata2.asl A src/soc/intel/snowridge/acpi/smbus.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/hob_iiouds.h A src/soc/intel/snowridge/hqm.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/itss.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pci_ids.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/memmap.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 73 files changed, 5,866 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 16 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 28 Aug '24

28 Aug '24

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Martin L Roth, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Hello Felix Held, Nicholas Chin, Nicholas Sudsgaard, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - 8GB LPDDR5 memory - 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup Testing with Lite carrier board - Booting into installed Windows 11: Passed - USB 3.0/2.0: Working - HDMI output: Working - Realtek Ethernet: Working - S3 sleep mode: Failed - Power on after shutdown: Failed (requires power removal) - Installing Ubuntu 22.04: Failed - UART of SuperIO in OS: Missing - Environment Controller: Not supported - M.2/M Key: Not working (booting failed with SSD 512GB installed) Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 21 files changed, 695 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 12 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 15: (7 comments) File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/d66d1020_8e5045f4?us… : PS15, Line 97: { maybe the common codes could be used (src/acpi/acpigen_pci_root_resource_producer.c) https://review.coreboot.org/c/coreboot/+/83321/comment/5cc43e20_196485cf?us… : PS15, Line 168: if (dev->path.type != DEVICE_PATH_DOMAIN || could use domain0 checker here. https://review.coreboot.org/c/coreboot/+/83321/comment/a18687c1_c3788585?us… : PS15, Line 174: uncore_fill_ssdt(); uncore usually indicates northcluster, a bit confusing here. https://review.coreboot.org/c/coreboot/+/83321/comment/70222886_dc5b3c0a?us… : PS15, Line 243: if (read32p(HPET_BASE_ADDRESS + 0x100) & 0x00008000) { are there macros for these constants? https://review.coreboot.org/c/coreboot/+/83321/comment/536997cb_53d64da8?us… : PS15, Line 277: } else if (stack == STACK2) { there includes some hardcodings, not sure if this could improved in future. e.g. to generate this based on pci enum results. https://review.coreboot.org/c/coreboot/+/83321/comment/4538833f_9c0b5d68?us… : PS15, Line 430: if (dev->upstream->secondary) /**< Write only for system agent in the first domain 0. */ could use the domain0 checker File src/soc/intel/snowridge/sriov.c: https://review.coreboot.org/c/coreboot/+/83321/comment/d86ea559_661fa090?us… : PS15, Line 12: not sure if this could be moved to common pci codes. -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 15 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 28 Aug 2024 07:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Felix Singer (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Martin L Roth, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Felix Singer has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 11: (1 comment) File src/mainboard/lattepanda/mu/spd/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83719/comment/40146455_6850b866?us… : PS11, Line 6: CI tests are failing because of these blank lines. Please remove -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 11 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Aug 2024 07:34:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, Felix Singer, Martin L Roth, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. KunYi Chen has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 10: (8 comments) File src/mainboard/lattepanda/mu/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83719/comment/554bc4b8_d0ffe526?us… : PS10, Line 9: register "emmc_enable_hs400_mode" = "1" > Move this setting below the emmc device from the devicetree. Acknowledged. okay, thanks https://review.coreboot.org/c/coreboot/+/83719/comment/8513ec13_2c21dd0d?us… : PS10, Line 11: register "sata_salp_support" = "0" > Settings are initialized with 0, please remove. Acknowledged. okay. remove it. just reference src/mainboard/intel/adlrvp/devicetree_n.cb https://review.coreboot.org/c/coreboot/+/83719/comment/3608fdd5_8d15d3a5?us… : PS10, Line 38: register "serial_io_gspi_cs_mode" = "{ : [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, : [PchSerialIoIndexGSPI3] = 0, : }" : : register "serial_io_gspi_cs_state" = "{ : [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, : [PchSerialIoIndexGSPI3] = 0, : }" > Settings are initialized with 0, please remove. Acknowledged, remove all. thanks https://review.coreboot.org/c/coreboot/+/83719/comment/a8339656_4f2ea050?us… : PS10, Line 59: register "pch_hda_dsp_enable" = "1" : register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" : register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" : r > Move these settings below the hda device from the devicetree. Acknowledged https://review.coreboot.org/c/coreboot/+/83719/comment/af0ee396_71c0b6a4?us… : PS10, Line 103: [3] = USB2_PORT_EMPTY, > USB ports are disabled by default, remove. Acknowledged, remove it. https://review.coreboot.org/c/coreboot/+/83719/comment/e1915565_bae8abea?us… : PS10, Line 110: [0] = USB3_PORT_EMPTY, : > Same here. Acknowledged, remove it. File src/mainboard/lattepanda/mu/spd/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83719/comment/a42b8fd7_bcf8b785?us… : PS10, Line 7: SPD_SOURCES += empty # 0b004 > This seems odd. […] Okay, I was just referencing src/mainboard/intel/adlrvp/spd/Makefile.mk After testing, it seems unnecessary. File src/mainboard/lattepanda/mu/spd/empty.spd.hex: PS10: > Why is a zeroed SPD file needed? Acknowledged, remove it -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 10 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Aug 2024 07:28:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Martin L Roth, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Hello Felix Held, Nicholas Chin, Nicholas Sudsgaard, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Nicholas Sudsgaard, Verified+1 by build bot (Jenkins) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - 8GB LPDDR5 memory - 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup Testing with Lite carrier board - Booting into installed Windows 11: Passed - USB 3.0/2.0: Working - HDMI output: Working - Realtek Ethernet: Working - S3 sleep mode: Failed - Power on after shutdown: Failed (requires power removal) - Installing Ubuntu 22.04: Failed - UART of SuperIO in OS: Missing - Environment Controller: Not supported - M.2/M Key: Not working (booting failed with SSD 512GB installed) Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 21 files changed, 696 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 11 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 15: (7 comments) File src/soc/intel/snowridge/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83321/comment/cb5be18a_8ec8ef32?us… : PS15, Line 22: #define GPIO_WEST2_PADCFGLOCKTX 0x00c4 Not sure if these cfg registers are the same across community/groups? If yes, if it is possible to only define one set of register offsets and applied for all community/groups by rebase? (what is did by gpio common codes) File src/soc/intel/snowridge/romstage/gpio_snr.c: https://review.coreboot.org/c/coreboot/+/83321/comment/3eb8034a_a45537bd?us… : PS15, Line 145: for (j = i + 1; j < num; j++) { this assumes the bits in the same group are placed together, if removing this assumption, will this code still work? https://review.coreboot.org/c/coreboot/+/83321/comment/e5d2be89_98fe497a?us… : PS15, Line 160: */ so the assumption is: only pad_config_mask covered bits are with explicit setting, while the not covered parts are left default, right? https://review.coreboot.org/c/coreboot/+/83321/comment/c3c71421_335fa683?us… : PS15, Line 207: if (comm_index != SNR_GPIO_COMMUNITY(gpio[j].cfg.pad) || if remove this assumption, there will be duplicated settings, but the result will be still correct. P.S. this assumption cannot remove all duplication cases (e.g. pads in the same community are scattered in the input list), maybe we can directly remove it? File src/soc/intel/snowridge/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/83321/comment/536c7ed1_dd329243?us… : PS15, Line 108: const FSP_SMBIOS_MEMORY_INFO *fsp_smbios_memory_info; to declare variable along with using will help the readability of the codes. https://review.coreboot.org/c/coreboot/+/83321/comment/dc156a3e_d5fa7bda?us… : PS15, Line 133: channel < ARRAY_SIZE(fsp_smbios_memory_info->ChannelInfo) && assume fsp_smbios_memory_info->ChannelCount == ARRAY_SIZE(fsp_smbios_memory_info->ChannelInfo)? https://review.coreboot.org/c/coreboot/+/83321/comment/89ac4f7e_acd9f3e2?us… : PS15, Line 139: dimm < ARRAY_SIZE(channel_info->DimmInfo) && assume dimm < channel_info->DimmCoun == dimm < ARRAY_SIZE(channel_info->DimmInfo)? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 15 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 28 Aug 2024 07:18:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/crossgcc: Patch clang to enable linking x86 bare metal targets
by Arthur Heymans (Code Review) 28 Aug '24

28 Aug '24

Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84032?usp=email ) Change subject: util/crossgcc: Patch clang to enable linking x86 bare metal targets ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: > Rolling out new toolchain on the build servers later. Thanks. I'm curious how the LTO series will fare with clang :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/84032?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Gerrit-Change-Number: 84032 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Aug 2024 07:07:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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