coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: Update intel-microcode submodule to upstream main
by Sean Rhodes (Code Review) 28 Aug '24

28 Aug '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84110?usp=email ) Change subject: Update intel-microcode submodule to upstream main ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cf5d78bcda07f742a8282b84a1c8336e6a23594 Gerrit-Change-Number: 84110 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 28 Aug 2024 08:28:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Paul Menzel (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Paul Menzel has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 66: (6 comments) Patchset: PS66: How did you create the ASL files? Copy from some datasheet? Write from scratch? Commit Message: https://review.coreboot.org/c/coreboot/+/83772/comment/e55d4db5_79b2a50a?us… : PS66, Line 12: wake up waking up or wakeup or wake-up https://review.coreboot.org/c/coreboot/+/83772/comment/45185627_1ef34539?us… : PS66, Line 14: , Not needed. https://review.coreboot.org/c/coreboot/+/83772/comment/cd4594e9_feec8213?us… : PS66, Line 16: gaurd guard https://review.coreboot.org/c/coreboot/+/83772/comment/8eb5f4a4_09c453d9?us… : PS66, Line 15: common/block/acpi/acpi/northbridge.asl binding with PTL change, : #if DMI_BASE_SIZE gaurd check is added in northbridge.asl Indent with one more space to align with above.? File src/soc/intel/pantherlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/356449d2_9d165da2?us… : PS66, Line 7: Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), : * USB device controller(xDCI) Please add a space before (. -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 66 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 08:27:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 56: (17 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/dccdcbc5_72c8a1b8?us… : PS55, Line 124: printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); > shouldn't we return when we have detected a NULL pointer? you have identified a NULL pointer and nex […] Added to return NULL. https://review.coreboot.org/c/coreboot/+/83798/comment/ad0b2bca_14264325?us… : PS55, Line 148: } > same Added to return NULL. https://review.coreboot.org/c/coreboot/+/83798/comment/0bde44b2_6eb9cb8a?us… : PS55, Line 161: } > same Added to return NULL. https://review.coreboot.org/c/coreboot/+/83798/comment/601eeda1_a0418b53?us… : PS55, Line 235: DEBUG_WILL > what you mean by `DEBUG_WILL` is this kind of macro ? Not a macro, String to indicate debug prints, corrected to use "DEBUG:" https://review.coreboot.org/c/coreboot/+/83798/comment/ebb87583_3e1c240a?us… : PS55, Line 240: DEBUG_WILL > same? Acknowledged https://review.coreboot.org/c/coreboot/+/83798/comment/2ef81a7c_08e8b9ab?us… : PS55, Line 347: } > why using NULL pointer w/o returning? Added to use return NULL. File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/5f3007e6_a21f42cf?us… : PS55, Line 46: 4Xe25W > this is 25W? Corrected to 15W. https://review.coreboot.org/c/coreboot/+/83798/comment/481d8d9d_6addd934?us… : PS55, Line 46: PTL_U_404_4_15W_CORE, /* 4 P-cores +0 E-cores + 4 LP E-cores + 4Xe25W*/ > one space after `+` Acknowledged https://review.coreboot.org/c/coreboot/+/83798/comment/0ad7e87a_0c261adc?us… : PS55, Line 49: PTL_H_484_45W_CORE > n You mean to say, this is not required? https://review.coreboot.org/c/coreboot/+/83798/comment/02b580b3_90f6c754?us… : PS55, Line 68: PCI_DID_INTEL_PTL_H_ID_2 > as per EDS this is 45W SOC part bt you have added this as 25W SKU Sure, i have updated the config to 45W. File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/ef7fc309_e881774d?us… : PS50, Line 43: PTL_U_404_15W_CORE, : PTL_H_484_25W_CORE, : PTL_H_484_45W_CORE, > > Hi Subrata, 404 means =(4 P-cores +0 E-cores + 4 LP […] Added. File src/soc/intel/pantherlake/chip.c: https://review.coreboot.org/c/coreboot/+/83798/comment/58df723d_12042e69?us… : PS55, Line 167: } > same , please return if NULL Added to return NULL. https://review.coreboot.org/c/coreboot/+/83798/comment/73cdba6a_28e62269?us… : PS55, Line 256: soc > pcd as well ? Sure, changed. File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/40fe6348_8a28838c?us… : PS55, Line 129: } > same Added return. https://review.coreboot.org/c/coreboot/+/83798/comment/3ad46438_867f644a?us… : PS55, Line 171: } > same Added return. File src/soc/intel/pantherlake/include/soc/p2sb.h: https://review.coreboot.org/c/coreboot/+/83798/comment/9b314b30_fa0c1977?us… : PS55, Line 12: soc_ > pcd Ack,changed. File src/soc/intel/pantherlake/p2sb.c: https://review.coreboot.org/c/coreboot/+/83798/comment/060ff668_e1374d28?us… : PS55, Line 47: soc_ > pcd Ack, changed. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 56 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 08:13:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#56). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,748 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/56 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 56 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Paul Menzel (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, Felix Singer, KunYi Chen, Martin L Roth, Nicholas Chin, Nicholas Sudsgaard. Paul Menzel has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 12: (2 comments) File src/mainboard/lattepanda/mu/board_info.txt: https://review.coreboot.org/c/coreboot/+/83719/comment/130045dd_90fa61c4?us… : PS12, Line 1: Vendor name: DFRobot Hmm, should the directory have the vendor included then? src/mainboard/dfrobot/lattepanda-mu File src/mainboard/lattepanda/mu/data.vbt: PS12: Please mention in the commit message, how you created this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 12 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Aug 2024 08:01:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Paul Menzel (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, Felix Singer, KunYi Chen, Martin L Roth, Nicholas Chin, Nicholas Sudsgaard. Paul Menzel has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 12: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83719/comment/650545b4_c37f619a?us… : PS8, Line 2: KunYi > 'Kun Yi' or 'KunYi', what's your mean? KunYi is my first name […] I see. It’s uncommon in “Western” sphere, to have CamelCase names. Often a space or hyphen is used. Commit Message: https://review.coreboot.org/c/coreboot/+/83719/comment/b87451a0_2da61912?us… : PS12, Line 20: Testing with Lite carrier board Please also list the payload (and version). -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 12 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Aug 2024 07:59:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: KunYi Chen <kunyi.chen(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/common/systemagent: read sa resources only from domain 0
by Name of user not set (Code Review) 28 Aug '24

28 Aug '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84109?usp=email ) Change subject: soc/intel/common/systemagent: read sa resources only from domain 0 ...................................................................... soc/intel/common/systemagent: read sa resources only from domain 0 Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/84109/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index bca442b..e8d7432 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -273,6 +273,12 @@ { int index = 0; + /** + * If SoC has multiple PCIe domains, only reading resources from the first one. + */ + if (!is_dev_on_domain0(dev)) + return; + /* Read standard PCI resources. */ pci_dev_read_resources(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/84109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305 Gerrit-Change-Number: 84109 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[S] Change in coreboot[main]: soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig
by Name of user not set (Code Review) 28 Aug '24

28 Aug '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84108?usp=email ) Change subject: soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig ...................................................................... soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig CAPID_A, BDSM and BGSM registers may not exist on specific platform, this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER` to select them. Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/84108/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 7bb55fe..42d579a 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -43,4 +43,16 @@ help Specify if the SOC has a PAM0 register +config HAVE_CAPID_A_REGISTER + bool + default y + help + Specify if the SOC has the CAPID0_A register that holds DRAM infomations. + +config HAVE_BDSM_BGSM_REGISTER + bool + default y + help + Specify if the SOC has BDSM and BGSM registres. + endif diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5d9ac15..bca442b 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -78,6 +78,9 @@ if (m == NULL) return; + if (!CONFIG(HAVE_CAPID_A_REGISTER)) + return; + const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A); m->ecc_type = sa_get_ecc_type(capid0_a); @@ -126,7 +129,9 @@ static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = { { TOUUD, true, "TOUUD" }, { TOLUD, false, "TOLUD" }, +#if CONFIG(HAVE_BDSM_BGSM_REGISTER) { BGSM, false, "BGSM" }, +#endif { TSEG, false, "TSEG" }, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 58d1113..e0f956b 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -58,7 +58,9 @@ enum { SA_TOUUD_REG, SA_TOLUD_REG, +#if CONFIG(HAVE_BDSM_BGSM_REGISTER) SA_BGSM_REG, +#endif SA_TSEG_REG, /* Must be last. */ MAX_MAP_ENTRIES -- To view, visit https://review.coreboot.org/c/coreboot/+/84108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Gerrit-Change-Number: 84108 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[M] Change in coreboot[main]: soc/intel/common/systemagent: fixup systemagent address
by Name of user not set (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, Felix Singer, Jérémy Compostella, Shuo Liu, yuchi.chen(a)intel.com. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent: fixup systemagent address ...................................................................... soc/intel/common/systemagent: fixup systemagent address System agent in Intel common block (1) assumes TOLUD and TOUUD registers hold the max available address plus 1, but on some SoC like Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD and TSEG registers to 1 MiB default, but some SoC may have different alignments. This patch add a new function soc_systemagent_fixup_address() to improve it. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 58 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 14 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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