coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

1 participants
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[XL] Change in coreboot[main]: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
by Maxim (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83107?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard ...................................................................... mb/asrock: Add Asrock Industrial IMB-1222 motherboard ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX motherboard [1]. Working: - Dual Channel DDR4 2933/2666/2400 MHz; - Intel UHD Graphics (VGA Option ROM, libgfxinit); - DP (both), HDMI; - PCIe x16 Slot (Gen3); - SATA ports; - USB 2.0 ports; - USB 3.0 ports; - M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi); - M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1); - M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3); - LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps; - LAN2 Intel I219LM, 10/100/1000 Mbps; - Realtek ALC887 HD Audio (line-out, mic-in); - COM 1/2/3/4 ports; - onboard speaker; - HWM/FANs control (fintek f81966); - S3 suspend and wake; - TPM; - disabling ME (me_cleaner); - boots Ubuntu 22.04/24.04 (SeaBIOS, Linuxboot, edk2 [2]). Unknown/untested: - USB3.0 in M.2 Key-B 3042/3052 slot; - eDP/LVDS; - PCIe riser cards; - SPDIF. Known issues: - there is no video output in firmware with edk2 [2]. There is no schematic/boardview, reverse engineering only. This port is based on system76/bonw14 because it has a similar topology. [1] https://web.archive.org/web/20220924171403/https:// www.asrockind.com/en-gb/IMB-1222 [2] MrChromebox' edk2 fork, https://github.com/mrchromebox/edk2 uefipayload_202309 branch Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A Documentation/mainboard/asrock/imb-1222.md M Documentation/mainboard/index.md A src/mainboard/asrock/imb-1222/Kconfig A src/mainboard/asrock/imb-1222/Kconfig.name A src/mainboard/asrock/imb-1222/Makefile.mk A src/mainboard/asrock/imb-1222/acpi/mainboard.asl A src/mainboard/asrock/imb-1222/acpi/sleep.asl A src/mainboard/asrock/imb-1222/board_info.txt A src/mainboard/asrock/imb-1222/bootblock.c A src/mainboard/asrock/imb-1222/cmos.default A src/mainboard/asrock/imb-1222/cmos.layout A src/mainboard/asrock/imb-1222/data.vbt A src/mainboard/asrock/imb-1222/devicetree.cb A src/mainboard/asrock/imb-1222/dsdt.asl A src/mainboard/asrock/imb-1222/gma-mainboard.ads A src/mainboard/asrock/imb-1222/gpio.c A src/mainboard/asrock/imb-1222/gpio_beep.c A src/mainboard/asrock/imb-1222/hda_verb.c A src/mainboard/asrock/imb-1222/include/mainboard/gpio.h A src/mainboard/asrock/imb-1222/include/mainboard/superio.h A src/mainboard/asrock/imb-1222/panic.c A src/mainboard/asrock/imb-1222/ramstage.c A src/mainboard/asrock/imb-1222/romstage.c A src/mainboard/asrock/imb-1222/superio.c 24 files changed, 1,298 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83107/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/83107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Gerrit-Change-Number: 83107 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: Makefile: Finish switch to Makefile.mk from .inc
by Felix Singer (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Singer. Felix Singer has uploaded a new patch set (#3) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/80130?usp=email ) Change subject: Makefile: Finish switch to Makefile.mk from .inc ...................................................................... Makefile: Finish switch to Makefile.mk from .inc Remove include of Makefile.inc files - they're gone. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If0dbc7ed204047b5575b303f57f6cf607f688ad9 --- M Makefile 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/80130/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0dbc7ed204047b5575b303f57f6cf607f688ad9 Gerrit-Change-Number: 80130 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add EINT support
by Hung-Te Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Jarried Lin. Hung-Te Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84026?usp=email ) Change subject: soc/mediatek/mt8196: Add EINT support ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8196/eint.c: https://review.coreboot.org/c/coreboot/+/84026/comment/9df6df82_93e80cc9?us… : PS8, Line 11: uint32_t Will this table be used in the boot block? If yes, we may need to think about how to compress it; for example changing uint32_t to uint8_t (and drop the eint_num since it's not a sparse matrix). -- To view, visit https://review.coreboot.org/c/coreboot/+/84026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Gerrit-Change-Number: 84026 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:25:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: reset usb hub in bootblock
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Jarried Lin, Mingjin Ge, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84024?usp=email ) Change subject: mb/google/rauru: reset usb hub in bootblock ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84024/comment/f329d42d_90c70286?us… : PS8, Line 8: > Explain why this needs to be done in bootblock. @jarried.lin@mediatek.com Please add ``` We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84024?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Gerrit-Change-Number: 84024 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:24:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add EINT support
by Yu-Ping Wu (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84026?usp=email ) Change subject: soc/mediatek/mt8196: Add EINT support ...................................................................... Patch Set 8: (2 comments) File src/soc/mediatek/mt8196/eint.c: https://review.coreboot.org/c/coreboot/+/84026/comment/a60fb5d4_57cb1d16?us… : PS8, Line 11: [4] Use a struct: ``` struct eint_info { uintptr_t base; // How about storing EINT_E_BASE directly? uint32_t index; uint32_t debounce; // Is this unused? }; ``` Note that `eint_num` is not needed, because we are already using it as the array index. https://review.coreboot.org/c/coreboot/+/84026/comment/ea41aa6a_8029ae23?us… : PS8, Line 13: {0, 2, 0, 1}, Can we put one entry `{a, b, c, d}` per line? -- To view, visit https://review.coreboot.org/c/coreboot/+/84026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Gerrit-Change-Number: 84026 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:20:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Name of user not set (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Singer, Jérémy Compostella, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/fc594874_7c1048d1?us… : PS3, Line 10: { > If not using weak, can I create a new spd. […] Sorry for the typo, I mean in `coreboot/src/soc/intel/common/block/smbus/Makefile.mk`, add something like this: ifneq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IMC),y) bootblock += spd.c romstage += spd.c ramstage += spd.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 13 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:17:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Fix timer reset in BL31
by Hung-Te Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Jarried Lin, Yidi Lin, Yu-Ping Wu. Hung-Te Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83928?usp=email ) Change subject: soc/mediatek/mt8196: Fix timer reset in BL31 ...................................................................... Patch Set 21: (1 comment) File src/soc/mediatek/mt8196/timer_prepare.c: https://review.coreboot.org/c/coreboot/+/83928/comment/c93894fb_fe901ab2?us… : PS21, Line 29: clrbits32p(SYSTIMER_BASE, COMP_FEATURE_MASK); > Actually, we should use `mtk_systimer->cntcr` instead. Here please write […] I'd recommend using SET32_BITFIELDS -- To view, visit https://review.coreboot.org/c/coreboot/+/83928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59 Gerrit-Change-Number: 83928 Gerrit-PatchSet: 21 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhanzhan Ge <zhanzhan.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:14:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/76a6f2dd_c3ae42da?us… : PS3, Line 367: pmc_clear_std_gpe_status > I would have implemented this logic in a more abstract way (w/ an assumption that we have either one Kconfig that tells me if GPE1 exists or use a macro as per https://review.coreboot.org/c/coreboot/+/84103/comment/39abef01_50206d52/ > > ``` > static void pmc_clear_std_gpe_status(void) > { > print_std_gpe0_sts(reset_std_gpe0_status()); > if (GPE1_STS(0)) > print_std_gpe1_sts(reset_std_gpe1_status()); > > } > ``` > > or > > ``` > static void pmc_clear_std_gpe_status(void) > { > print_std_gpe0_sts(reset_std_gpe0_status()); > if (SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) > print_std_gpe1_sts(reset_std_gpe1_status()); > > } > ``` or maybe something like this ? then you don't need to pass `_gpeX_` for each functions ``` static void pmc_clear_std_gpe_status(void) { print_std_gpe0_sts(reset_std_gpe_status(0)); if (GPE1_STS(0)) print_std_gpe1_sts(reset_std_gpe_status(1)); } ``` or ``` static void pmc_clear_std_gpe_status(void) { print_std_gpe0_sts(reset_std_gpe_status(0)); if (SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) print_std_gpe1_sts(reset_std_gpe_status(1)); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:13:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: add unmask eint event for bootblock
by Yu-Ping Wu (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: add unmask eint event for bootblock ...................................................................... Patch Set 8: (3 comments) File src/soc/mediatek/mt8196/eint_event.c: https://review.coreboot.org/c/coreboot/+/84025/comment/f3519321_0d863f86?us… : PS8, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ One blank line below. File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/84025/comment/4391a309_1c6d57d1?us… : PS8, Line 13: tabs File src/soc/mediatek/mt8196/include/soc/eint_event.h: https://review.coreboot.org/c/coreboot/+/84025/comment/84af1a37_22a29835?us… : PS8, Line 16: unmask eint event, eint can wakeup by spm `Unmask eint event, which can be woken up by SPM.` -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:09:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/hp: Add Compaq Elite 8300 CMT port
by Felix Singer (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Nicholas Chin, Nico Huber, Paul Menzel, Riku Viitanen. Felix Singer has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/79745?usp=email ) Change subject: mb/hp: Add Compaq Elite 8300 CMT port ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: Hi @riku.viitanen@protonmail.com, are you interested in finishing this port? Also, could you move it into snb_ivb_desktops as a variant? -- To view, visit https://review.coreboot.org/c/coreboot/+/79745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Gerrit-Change-Number: 79745 Gerrit-PatchSet: 17 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 06:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit August 2024