coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Nicholas Sudsgaard (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, Felix Singer, KunYi Chen, Martin L Roth, Nicholas Chin, Paul Menzel. Nicholas Sudsgaard has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 13: Code-Review+1 (1 comment) File src/mainboard/lattepanda/mu/mainboard.c: https://review.coreboot.org/c/coreboot/+/83719/comment/a011b04a_12b960fb?us… : PS13, Line 46: co Is this necessary? It seems like the default. -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 13 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Aug 2024 11:15:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules
by Krystian Hebel (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Patrick Rudolph, Sergii Dmytruk. Krystian Hebel has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83422?usp=email ) Change subject: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Gerrit-Change-Number: 83422 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 10:11:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yu-Ping Wu. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84115?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ...................................................................... soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8195/include/soc/pcie.h M src/soc/mediatek/mt8195/pcie.c 5 files changed, 15 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84115/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Gerrit-Change-Number: 84115 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/common/pcie: Add mtk_pcie_deassert_perst for early PCIE ...
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yu-Ping Wu. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84117?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/common/pcie: Add mtk_pcie_deassert_perst for early PCIE reset ...................................................................... soc/mediatek/common/pcie: Add mtk_pcie_deassert_perst for early PCIE reset Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47 waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIE reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c 2 files changed, 54 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84117/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIE reset in romstage
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84118?usp=email ) Change subject: mb/google/cherry: Complete PCIE reset in romstage ...................................................................... mb/google/cherry: Complete PCIE reset in romstage De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIE early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIE early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.mk 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/84118/1 diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index f375867..ab05220 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -8,6 +8,7 @@ #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/mt6360.h> +#include <soc/pcie.h> #include <soc/pll_common.h> #include <soc/pmif.h> #include <soc/rtc.h> @@ -33,6 +34,8 @@ mt6360_init(I2C7); clk_buf_init(); rtc_boot(); + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); mtk_dram_init(); scp_rsi_enable(); } diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index a37f715..a3b002e 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -36,6 +36,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += mt6360.c romstage-y += mt6691.c +romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += apusys.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: pcie: Add mtk_pcie_deassert_perst for early PCIE reset
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84117?usp=email ) Change subject: soc/mediatek: pcie: Add mtk_pcie_deassert_perst for early PCIE reset ...................................................................... soc/mediatek: pcie: Add mtk_pcie_deassert_perst for early PCIE reset Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47 waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIE reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c 2 files changed, 54 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84117/1 diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index dc3208d..cb47f7f 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -23,5 +23,6 @@ void mtk_pcie_domain_set_resources(struct device *dev); void mtk_pcie_domain_enable(struct device *dev); void mtk_pcie_reset(uintptr_t reg, bool enable); +void mtk_pcie_deassert_perst(void); #endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index 9b289c5..4972492 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -266,24 +266,9 @@ return CB_SUCCESS; } -void mtk_pcie_domain_enable(struct device *dev) +static void wait_perst_asserted(uintptr_t base) { - const mtk_soc_config_t *config = config_of(dev); - const struct mtk_pcie_config *conf = &config->pcie_config; - const char *ltssm_state; long perst_time_us; - size_t tries = 0; - uint32_t val; - - /* Set as RC mode */ - setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE); - - /* Set class code */ - clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8), - PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); - - /* Mask all INTx interrupts */ - clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n", @@ -301,7 +286,7 @@ printk(BIOS_WARNING, "%s: PCIe early init data not found, sleeping 100ms\n", __func__); - mtk_pcie_reset(conf->base, true); + mtk_pcie_reset(base, true); } else { printk(BIOS_WARNING, "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", @@ -310,9 +295,59 @@ udelay(min_perst_time_us - perst_time_us); } +} +static void deassert_perst(uintptr_t base) +{ + /* Set as RC mode */ + setbits32p(base + PCIE_SETTING_REG, PCIE_RC_MODE); + + /* Set class code */ + clrsetbits32p(base + PCIE_PCI_IDS_1, GENMASK(31, 8), + PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); + + /* Mask all INTx interrupts */ + clrbits32p(base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); + + /* Above registers must be set before de-asserting PERST# */ /* De-assert reset signals */ - mtk_pcie_reset(conf->base, false); + mtk_pcie_reset(base, false); +} + +static void wait_perst_done(uintptr_t base) +{ + long perst_time_us; + + wait_perst_asserted(base); + + perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE_RESET); + printk(BIOS_DEBUG, "%s: %ld us elapsed since de-assert PERST#\n", + __func__, perst_time_us); + + if (!perst_time_us) { + printk(BIOS_INFO, "%s: PCIE early PERST# de-assertion is not done, " + "de-assert PERST# now\n", __func__); + deassert_perst(base); + } +} + +void mtk_pcie_deassert_perst(void) +{ + uintptr_t base = mtk_pcie_get_controller_base(0); + + wait_perst_done(base); + early_init_save_time(EARLY_INIT_PCIE_RESET); +} + +void mtk_pcie_domain_enable(struct device *dev) +{ + const mtk_soc_config_t *config = config_of(dev); + const struct mtk_pcie_config *conf = &config->pcie_config; + const char *ltssm_state; + size_t tries = 0; + uint32_t val; + + wait_perst_done(conf->base); if (!retry(100, (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_type
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84116?usp=email ) Change subject: soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_type ...................................................................... soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_type Add EARLY_INIT_PCIE_RESET for early PERST# de-assertion. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/early_init.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/84116/1 diff --git a/src/soc/mediatek/common/include/soc/early_init.h b/src/soc/mediatek/common/include/soc/early_init.h index 533dffd..0c4582f 100644 --- a/src/soc/mediatek/common/include/soc/early_init.h +++ b/src/soc/mediatek/common/include/soc/early_init.h @@ -12,6 +12,7 @@ enum early_init_type { EARLY_INIT_PCIE, + EARLY_INIT_PCIE_RESET, EARLY_INIT_MAX, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716 Gerrit-Change-Number: 84116 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84115?usp=email ) Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ...................................................................... soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8195/include/soc/pcie.h M src/soc/mediatek/mt8195/pcie.c 5 files changed, 15 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84115/1 diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index 0f02ab7..dc3208d 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -22,5 +22,6 @@ void mtk_pcie_domain_read_resources(struct device *dev); void mtk_pcie_domain_set_resources(struct device *dev); void mtk_pcie_domain_enable(struct device *dev); +void mtk_pcie_reset(uintptr_t reg, bool enable); #endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index 39714e1..9b289c5 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -247,6 +247,16 @@ pci_domain_set_resources(dev); } +void mtk_pcie_reset(uintptr_t base, bool enable) +{ + uint32_t flags = PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; + + if (enable) + setbits32p(base + PCIE_RST_CTRL_REG, flags); + else + clrbits32p(base + PCIE_RST_CTRL_REG, flags); +} + enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { if (!pci_root_bus()) @@ -291,7 +301,7 @@ printk(BIOS_WARNING, "%s: PCIe early init data not found, sleeping 100ms\n", __func__); - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(conf->base, true); } else { printk(BIOS_WARNING, "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", @@ -302,7 +312,7 @@ } /* De-assert reset signals */ - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); + mtk_pcie_reset(conf->base, false); if (!retry(100, (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 3446144..a37f715 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -13,7 +13,7 @@ bootblock-y += ../common/early_init.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/mmu_operations.c -bootblock-$(CONFIG_PCI) += pcie.c +bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h index 117f4cc..75c52c1 100644 --- a/src/soc/mediatek/mt8195/include/soc/pcie.h +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -6,7 +6,6 @@ #include <soc/pcie_common.h> #include <types.h> -void mtk_pcie_reset(uintptr_t reg, bool enable); void mtk_pcie_pre_init(void); bool mainboard_needs_pcie_init(void); diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index eb7ad87..2676207 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -9,11 +9,6 @@ #include <soc/pcie_common.h> #define PCIE_REG_BASE_PORT0 0x112f0000 -#define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) -#define PCIE_MAC_RSTB BIT(0) -#define PCIE_PHY_RSTB BIT(1) -#define PCIE_BRG_RSTB BIT(2) -#define PCIE_PE_RSTB BIT(3) struct pad_func { gpio_t gpio; @@ -46,28 +41,12 @@ } } -void mtk_pcie_reset(uintptr_t reg, bool enable) -{ - uint32_t val; - - val = read32p(reg); - - if (enable) - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - else - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - - write32p(reg, val); -} - void mtk_pcie_pre_init(void) { mtk_pcie_set_pinmux(0); /* Assert all reset signals at early stage */ - mtk_pcie_reset(PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(PCIE_REG_BASE_PORT0, true); early_init_save_time(EARLY_INIT_PCIE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Gerrit-Change-Number: 84115 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common/pcie: Use clr/setbits32p
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84114?usp=email ) Change subject: soc/mediatek/common/pcie: Use clr/setbits32p ...................................................................... soc/mediatek/common/pcie: Use clr/setbits32p Use clr/setbits32p to make code cleaner. BUG=none TEST=emerge-cherry coreboot Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/pcie.c 1 file changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/84114/1 diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c07cc4f..39714e1 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -266,20 +266,14 @@ uint32_t val; /* Set as RC mode */ - val = read32p(conf->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(conf->base + PCIE_SETTING_REG, val); + setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE); /* Set class code */ - val = read32p(conf->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(conf->base + PCIE_PCI_IDS_1, val); + clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8), + PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); /* Mask all INTx interrupts */ - val = read32p(conf->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(conf->base + PCIE_INT_ENABLE_REG, val); + clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/84114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Gerrit-Change-Number: 84114 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common/pcie: Add DEVTREE_CONST qualifier
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84113?usp=email ) Change subject: soc/mediatek/common/pcie: Add DEVTREE_CONST qualifier ...................................................................... soc/mediatek/common/pcie: Add DEVTREE_CONST qualifier Fix the compilation error for ``` src/soc/mediatek/common/pcie.c:104:26: error: assignment discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] 104 | root_dev = pcidev_path_on_root(devfn); | ^ ``` BUG=none TEST=emerge-cherry coreboot Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/84113/1 diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index ce9055a..c07cc4f 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -96,7 +96,7 @@ static uintptr_t mtk_pcie_get_controller_base(pci_devfn_t devfn) { - struct device *root_dev; + DEVTREE_CONST struct device *root_dev; const mtk_soc_config_t *config; static uintptr_t base = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/84113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e Gerrit-Change-Number: 84113 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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