coreboot-gerrit August 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#60). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,742 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/60 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 60 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/apl: Fix building with clang & LTO
by Sean Rhodes (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Arthur Heymans. Sean Rhodes has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84047?usp=email ) Change subject: soc/intel/apl: Fix building with clang & LTO ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Gerrit-Change-Number: 84047 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Aug 2024 13:40:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: [WIP] payloads/Linuxboot: Fix u-root build
by Maximilian Brune (Code Review) 28 Aug '24

28 Aug '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84119?usp=email ) Change subject: [WIP] payloads/Linuxboot: Fix u-root build ...................................................................... [WIP] payloads/Linuxboot: Fix u-root build Currently u-root doesn't build for various reasons. 1. The boot cmds have changed. Some have been removed and the default has changed to the 'boot' cmd for loading an OS. 2. The elvish shell has been removed as default shell. The gosh is now the default. 3. For some reason the -uroot-source parameter doesn't exist anymore? So instead we just cd into the u-root directory and build the initramfs there. Build tested: | CONFIG_LINUXBOOT_COMPILE_KERNEL | CONFIG_LINUXBOOT_BUILD_INITRAMFS | ---------------------------------------------------------------------- | n | n | | n | y | | y | n | | y | y | ---------------------------------------------------------------------- Change-Id: If66238cec248deb3594de82f3adbc608516a2fc5 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.mk 4 files changed, 38 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84119/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 454b7c5..728eee3 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -57,8 +57,8 @@ config LINUXBOOT_KERNEL_PATH string "Path to kernel" - default "build/uImage" if LINUXBOOT_KERNEL_UIMAGE - default "build/bzImage" if LINUXBOOT_KERNEL_BZIMAGE + default "" + depends on !LINUXBOOT_COMPILE_KERNEL help The kernel path is either and absolute path or relative to the LinuxBoot directory @@ -142,7 +142,7 @@ config LINUXBOOT_INITRAMFS_PATH string "Path to initramfs" - default "build/initramfs_u-root.cpio" if LINUXBOOT_UROOT + default "payloads/external/LinuxBoot/build/initramfs" if LINUXBOOT_UROOT if LINUXBOOT_BUILD_INITRAMFS @@ -248,7 +248,7 @@ config LINUXBOOT_UROOT_SHELL string "default shell" - default "elvish" + default "gosh" help Default shell. Can be an absolute path or a u-root command name. (default "elvish") @@ -264,10 +264,10 @@ choice prompt "Choose a specific bootloader" - default SPECIFIC_BOOTLOADER_SYSTEMBOOT + default SPECIFIC_BOOTLOADER_BOOT help Specify a bootloader which starts after u-root init. It will be a symlink - to /bin/uinit. Default: systemboot + to /bin/uinit. Default: boot config SPECIFIC_BOOTLOADER_NONE bool "none" @@ -275,21 +275,14 @@ Leave u-root to decide which bootloaders to load first after init, if any at all. Most likely u-root will start into the defined u-root shell. -config SPECIFIC_BOOTLOADER_SYSTEMBOOT - bool "systemboot" - help - If systemboot has been used as a bootloader wrapper in the past, - enable this option. It will invoke -uinitcmd=systemboot and result in - a BIOS/UEFI BDS boot behavior. - -config SPECIFIC_BOOTLOADER_BOOT2 - bool "boot2" +config SPECIFIC_BOOTLOADER_BOOT + bool "boot" config SPECIFIC_BOOTLOADER_PXEBOOT bool "pxeboot" -config SPECIFIC_BOOTLOADER_STBOOT - bool "stboot" +config SPECIFIC_BOOTLOADER_FITBOOT + bool "fitboot" config SPECIFIC_BOOTLOADER_CUSTOM bool "custom" @@ -328,6 +321,7 @@ config LINUXBOOT_INITRAMFS_COMPRESSION_XZ bool "xz compression" + depends on LINUXBOOT_BUILD_INITRAMFS endchoice diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index fc2c818..83b8d6e 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -10,10 +10,6 @@ LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv -build/Image: $(CONFIG_LINUXBOOT_KERNEL_PATH) | build - ln -s -r $< $@ - - ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y) include targets/linux.mk endif @@ -21,30 +17,32 @@ include targets/u-root.mk endif -ifeq ($(CONFIG_LINUXBOOT_BUILD_INITRAMFS),y) -build/initramfs: $(CONFIG_LINUXBOOT_INITRAMFS_PATH) | build -else -build/initramfs: -endif -ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y) - xz --keep --force --check=crc32 --lzma2=dict=1MiB $(CONFIG_LINUXBOOT_INITRAMFS_PATH) -endif - cp $(CONFIG_LINUXBOOT_INITRAMFS_PATH)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) $@ - ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y) -build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage build/initramfs | build +build/Image: $(kernel_dir)/arch/x86/boot/bzImage | build cp $< $@ else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y) -build/target.dtb: $(CONFIG_LINUXBOOT_DTS_FILE) +build/target.dtb: $(CONFIG_LINUXBOOT_DTS_FILE) | build $(DTC) -o $@ $< -build/uImage: build/vmlinux.bin.lzma build/initramfs build/target.dtb $(LINUX_ARCH-y)/kernel_fdt_lzma.its | build +build/Image: build/vmlinux.bin.lzma build/initramfs build/target.dtb $(LINUX_ARCH-y)/kernel_fdt_lzma.its | build mkimage -f $(LINUX_ARCH-y)/kernel_fdt_lzma.its $@ -endif # CONFIG_LINUXBOOT_KERNEL_BZIMAGE +else ifneq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y) + +build/Image: $(CONFIG_LINUXBOOT_KERNEL_PATH) | build + cp $< $@ + +endif + +build/initramfs: build/initramfs_u-root.cpio | build +ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y) + xz --stdout --keep --force --check=crc32 --lzma2=dict=1MiB $< > $@ +else + cp $< $@ +endif build: mkdir build diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index 90b48ea..158a605 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -39,12 +39,13 @@ git clone https://$(uroot_package) $(uroot_build) git -C $(uroot_build) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION) -$(uroot_build)/u-root: $(uroot_build) +$(uroot_build)/u-root: | $(uroot_build) cd $(uroot_build); \ go build -o u-root . -#$(CONFIG_LINUXBOOT_INITRAMFS_PATH) build/initramfs_u-root.cpio: $(uroot_build)/u-root - GOARCH=$(UROOT_ARCH-y) $(uroot_build)/u-root \ - -uroot-source $(uroot_build) \ - $(uroot_args) -o build/initramfs_u-root.cpio $(uroot_cmds) + cd $(uroot_build); \ + echo "GOARCH=$(UROOT_ARCH-y) ./u-root $(uroot_args) -o initramfs_u-root.cpio $(uroot_cmds)" + cd $(uroot_build); \ + GOARCH=$(UROOT_ARCH-y) ./u-root $(uroot_args) -o initramfs_u-root.cpio $(uroot_cmds) + cp $(uroot_build)/initramfs_u-root.cpio $@ diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index ac5c856..86fa444 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -26,8 +26,8 @@ endif ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH))),) ifneq ($(CONFIG_LINUXBOOT_ARM64),y) - ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) - prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS))) + ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH) + prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH))) endif endif endif @@ -397,7 +397,7 @@ endif # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH endif # CONFIG_LINUXBOOT_CROSS_COMPILE .PHONY: linuxboot -payloads/external/LinuxBoot/build/Image linuxboot: +payloads/external/LinuxBoot/build/Image payloads/external/LinuxBoot/build/initramfs linuxboot: $(MAKE) -C payloads/external/LinuxBoot \ CPUS=$(CPUS) \ CONFIG_LINUXBOOT_X86_64=$(CONFIG_LINUXBOOT_X86_64) \ @@ -409,7 +409,6 @@ CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH) \ CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \ CONFIG_LINUXBOOT_INITRAMFS_PATH=$(CONFIG_LINUXBOOT_INITRAMFS_PATH) \ - CONFIG_LINUXBOOT_INITRAMFS_SUFFIX=$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) \ CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=$(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ) \ CONFIG_LINUXBOOT_COMPILE_KERNEL=$(CONFIG_LINUXBOOT_COMPILE_KERNEL) \ CONFIG_LINUXBOOT_KERNEL_PATH=$(CONFIG_LINUXBOOT_KERNEL_PATH) \ @@ -425,7 +424,8 @@ CONFIG_LINUXBOOT_UROOT_SHELL=$(CONFIG_LINUXBOOT_UROOT_SHELL) \ CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \ CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \ - CONFIG_LINUXBOOT_DTS_FILE=$(CONFIG_LINUXBOOT_DTS_FILE) + CONFIG_LINUXBOOT_DTS_FILE=$(CONFIG_LINUXBOOT_DTS_FILE) \ + $(subst payloads/external/LinuxBoot/,,$@) # BOOTBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/84119?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If66238cec248deb3594de82f3adbc608516a2fc5 Gerrit-Change-Number: 84119 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 59: (7 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/4eeffe2d_cf3751a1?us… : PS59, Line 117: static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), : ARRAY_SIZE(cstate_set_non_s0ix))] = { {0} }; > this is local variable and then declared as static. why you need to initialize it with zero ? […] Sure, valid point. Removing the assigment. https://review.coreboot.org/c/coreboot/+/83798/comment/486471d6_9446abc4?us… : PS59, Line 125: map > why ? you should return NULL here and update the common code to handle the NULL code […] Hi Subrata, will it also be requiring to make changes in other SOC platforms which are using generate_c_state_entries? Such as MTL, ADL, etc? https://review.coreboot.org/c/coreboot/+/83798/comment/9245f003_cccd41d2?us… : PS59, Line 243: printk(BIOS_DEBUG, "DMAR engine1 ACPI added\n"); > please drop this. […] Removed. https://review.coreboot.org/c/coreboot/+/83798/comment/a461e5c2_88669723?us… : PS59, Line 257: printk(BIOS_DEBUG, "DMAR engine2 ACPI added\n"); > same Removed. https://review.coreboot.org/c/coreboot/+/83798/comment/3091abae_684b9153?us… : PS59, Line 274: printk(BIOS_DEBUG, "DMAR engine3 ACPI added\n"); > same Removed. https://review.coreboot.org/c/coreboot/+/83798/comment/91829baa_38913f29?us… : PS59, Line 291: printk(BIOS_DEBUG, "DMAR RMRR ACPI added\n"); > same Removed. https://review.coreboot.org/c/coreboot/+/83798/comment/90011289_cfea0280?us… : PS59, Line 305: printk(BIOS_DEBUG, "SATC ACPI added\n"); > same Removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 59 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 12:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 59: (8 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/649bc21e_79575094?us… : PS59, Line 117: static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), : ARRAY_SIZE(cstate_set_non_s0ix))] = { {0} }; this is local variable and then declared as static. why you need to initialize it with zero ? array elements would be default assigned to zero w/o any explicit assignment https://review.coreboot.org/c/coreboot/+/83798/comment/0223af74_04eac8eb?us… : PS59, Line 125: map why ? you should return NULL here and update the common code to handle the NULL code ``` static void generate_c_state_entries(void) { const acpi_cstate_t *c_state_map; size_t entries; c_state_map = soc_get_cstate_map(&entries); if (c_state_map == NULL) return; /* Generate C-state tables */ acpigen_write_CST_package(c_state_map, entries); } ``` https://review.coreboot.org/c/coreboot/+/83798/comment/fcd857a3_b9077ece?us… : PS59, Line 243: printk(BIOS_DEBUG, "DMAR engine1 ACPI added\n"); please drop this. seems redundant https://review.coreboot.org/c/coreboot/+/83798/comment/0eaeac75_629a443d?us… : PS59, Line 257: printk(BIOS_DEBUG, "DMAR engine2 ACPI added\n"); same https://review.coreboot.org/c/coreboot/+/83798/comment/ce0fd7be_db64efac?us… : PS59, Line 272: 0x4 did you ignore my comments to use macro rather using hardcoded values ? https://review.coreboot.org/c/coreboot/+/83798/comment/04be5a2e_acadf0e3?us… : PS59, Line 274: printk(BIOS_DEBUG, "DMAR engine3 ACPI added\n"); same https://review.coreboot.org/c/coreboot/+/83798/comment/9f992ed7_1fdb2866?us… : PS59, Line 291: printk(BIOS_DEBUG, "DMAR RMRR ACPI added\n"); same https://review.coreboot.org/c/coreboot/+/83798/comment/37757897_a420393e?us… : PS59, Line 305: printk(BIOS_DEBUG, "SATC ACPI added\n"); same -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 59 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 12:28:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#59). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,747 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/59 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 59 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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