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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Shelley Chen, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83752?usp=email
to look at the new patch set (#16).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1.Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/chip.h
4 files changed, 83 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/16
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Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email )
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 15:
(2 comments)
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/98c555bd_20e8b80f?us… :
PS14, Line 32: FSPM_MAX_NONTURBO_FREQ
> > Last time I enquired PnP team they mentioned that P1 frequency and Boot frequency are different . […]
I have added comment with respect to this in the partnerbug Subrata - please take a look
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/ed2f65e1_6ce97644?us… :
PS8, Line 365: BootFrequency
> > In CPU soft strap I can see only processor boot at p1 frequency which is set as yes […]
Please take a look at the partnerbug subrata - I have tried to explain it in detail there
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Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email )
Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/84103/comment/5559dc40_1e66d002?us… :
PS3, Line 110: SOC_INTEL_COMMON_BLOCK_ACPI_GPE1
> Hi Subrata,
>
> I've looked into this approach of using GPE1_STS as conditional flag. GPE1_STS/EN will need to be added for the existing SOC headers. And these headers are SOC pm.h,
> where GPE0_STS/_EN() are defined. But, this header is not included in the ASL files. Currently, we only include SOC gpe.h. In the ASL, we were to use this new _GPE1 kconfig to determine the _Lxx events and add the event methods accordingly.
> In addition, the same Kconfig is to be used to determine whether GPE0 or GPE1 event bit is used in the devicetree. For instance:
>
> device ref cnvi_wifi on
> chip drivers/wifi/generic
> register "wake" = "CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) ? GPE1_CNVI_PME_B0 : GPE0_PME_B0"
> device generic 0 on end
> end
> end
>
> Also, even with GPE1 support, we might want o switch back to merely use the aggregated GPE0 STD events if any of fine GPE1 bit event not working or for debug purpose. The Kconfig might be preferred in this case.
>
> Should we add these two patches as part of our PTL upstream CLs so that I can add the corresponding SOC and MB GPE1 CLs for the complete view of this intension? or I can also include the related changed files in the cros bug 362310295? Please let me know.
I'm unable to follow the comments. what I'm suggesting is as gpe1_blk is not something new in ACPI spec hence, we might not need to apply a CPP. Rather you can use a zero value for existing SoC and value offset value for PTL SoC to avoid the CPP.
As an alternative if you wish to make use of Kconfig for keeping CPP, then please use the meaningful name.
Also, I'm unable to follow why you need a ternary operator in devicetree. if you know that PTL SOC supports gpe1_blk then you should be using GPE1_CNVI_PME_B0 over
GPE0_PME_B0.
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Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/84103/comment/8149abbb_60e31ec5?us… :
PS3, Line 110: SOC_INTEL_COMMON_BLOCK_ACPI_GPE1
> suggestion, looks like we don't need a CPP if we follow the below method […]
Hi Subrata,
I've looked into this approach of using GPE1_STS as conditional flag. GPE1_STS/EN will need to be added for the existing SOC headers. And these headers are SOC pm.h,
where GPE0_STS/_EN() are defined. But, this header is not included in the ASL files. Currently, we only include SOC gpe.h. In the ASL, we were to use this new _GPE1 kconfig to determine the _Lxx events and add the event methods accordingly.
In addition, the same Kconfig is to be used to determine whether GPE0 or GPE1 event bit is used in the devicetree. For instance:
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) ? GPE1_CNVI_PME_B0 : GPE0_PME_B0"
device generic 0 on end
end
end
Also, even with GPE1 support, we might want o switch back to merely use the aggregated GPE0 STD events if any of fine GPE1 bit event not working or for debug purpose. The Kconfig might be preferred in this case.
Should we add these two patches as part of our PTL upstream CLs so that I can add the corresponding SOC and MB GPE1 CLs for the complete view of this intension? or I can also include the related changed files in the cros bug 362310295? Please let me know.
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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS1:
> Correct. This is used in standalone environment. […]
Acknowledged
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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
File payloads/external/depthcharge/Kconfig:
https://review.coreboot.org/c/coreboot/+/84107/comment/731a49f3_3df6c6d8?us… :
PS4, Line 70: The Depthcharge makefile looks for a file config.<boardname> in the
: libpayload/configs directory. Say Y here to use the file defconfig
: instead. This is can be a convenience for development purposes, or
: if the defaults in defconfig are sufficient for your system.
> sure. updated.
Acknowledged
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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 4:
(2 comments)
File payloads/external/depthcharge/Kconfig:
https://review.coreboot.org/c/coreboot/+/84107/comment/4a6f79a4_c2d92c7e?us… :
PS4, Line 68: default n if LP_DEFCONFIG_OVERRIDE
> I don't believe you need this line. […]
Done
https://review.coreboot.org/c/coreboot/+/84107/comment/5a4c88ab_82e138ad?us… :
PS4, Line 70: The Depthcharge makefile looks for a file config.<boardname> in the
: libpayload/configs directory. Say Y here to use the file defconfig
: instead. This is can be a convenience for development purposes, or
: if the defaults in defconfig are sufficient for your system.
> this should somehow convey that one needs to select this config to boot a 64-bit payload
sure. updated.
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