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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84104/comment/5026318e_8c07f831?us… :
PS3, Line 10: ppe0
gpe0
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/1a1b7f2d_7f911234?us… :
PS3, Line 367: pmc_clear_std_gpe_status
> > I would have implemented this logic in a more abstract way (w/ an assumption that we have either o […]
I like this idea to use a single api to clear std gpe0 and gpe1.
https://review.coreboot.org/c/coreboot/+/84104/comment/b2a7d820_60c7c6d2?us… :
PS3, Line 368: gpi
pmc_clear_std_gpe1_status?
https://review.coreboot.org/c/coreboot/+/84104/comment/ff668c99_d3a05e0a?us… :
PS3, Line 393: void pmc_clear_std_gpe1_status
> Can this be instead pmc_clear_gpe1_status ? Unlike GPE0, you don't need the STD offset to be handled […]
I think all gpe1 registers are like standard gpe0 register, so naming with std looks okay.
https://review.coreboot.org/c/coreboot/+/84104/comment/f77a1e63_4be518bf?us… :
PS3, Line 406: pmc_clear_gpi_gpe0_status
> why you don't need to clean GPE1 status?
I think pmc_clear_std_gpe1_status is gonna clear all GPE1 registers, so wondering if anything missing.
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Attention is currently required from: Alper Nebi Yasak.
Paul Menzel has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/82065?usp=email )
Change subject: drivers/qemu/cirrus: Allow building for non-x86 architectures
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82065/comment/344cdea4_91a04b7f?us… :
PS2, Line 20: architectrures
architectures
https://review.coreboot.org/c/coreboot/+/82065/comment/8a7c77e6_5ecd7738?us… :
PS2, Line 23:
It’d be great, if you could add the command how to test this.
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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 5:
(1 comment)
File payloads/external/depthcharge/Kconfig:
https://review.coreboot.org/c/coreboot/+/84107/comment/44308859_b438ae2d?us… :
PS5, Line 71: This is can be a convenience for
: development purposes
Maybe:
> This can be convenient for development
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Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84120/comment/370e0197_dbf6e8bf?us… :
PS1, Line 16: logging
logged?
File src/vendorcode/google/chromeos/elog.c:
https://review.coreboot.org/c/coreboot/+/84120/comment/7286b388_0dbbf66a?us… :
PS1, Line 13: /*
: * Skip logging boot info if CSE sync scheduled at payload.
: * The payload should log boot info after CSE sync.
: */
Please align the comment asterisks correctly.
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Change subject: [RFC] Add UPL FDT handoff
......................................................................
Patch Set 21:
(1 comment)
File payloads/libpayload/arch/arm/coreboot.c:
https://review.coreboot.org/c/coreboot/+/76591/comment/597d2da2_6ba29e36?us… :
PS17, Line 60: if (CONFIG(LP_UPL))
> Sure but you would always need to compile in both handoffs. Not sure if that is worth the tradeoff.
Done
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Attention is currently required from: Arthur Heymans, Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Maximilian Brune, Philipp Hug, Simon Glass, ron minnich.
Hello Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Philipp Hug, Simon Glass, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC] Add UPL FDT handoff
......................................................................
[RFC] Add UPL FDT handoff
This adds another handoff that is basically the same as coreboot tables.
The only real difference is that it uses the devicetree format to
transfer the information to payload.
This handoff is inspired by the UPL (universal payload) specification.
Tested: start q35 qemu with coreinfo as payload and see that console
still works and the devicetree is printed by coreboot.
Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M payloads/Kconfig
M payloads/libpayload/arch/arm/coreboot.c
M payloads/libpayload/arch/arm64/coreboot.c
M payloads/libpayload/arch/x86/coreboot.c
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/Makefile.mk
A payloads/libpayload/libc/upl_fdt.c
M src/arch/arm/include/arch/cbconfig.h
M src/arch/arm64/include/arch/cbconfig.h
M src/arch/ppc64/include/arch/cbconfig.h
M src/arch/riscv/include/arch/cbconfig.h
M src/arch/x86/include/arch/cbconfig.h
M src/arch/x86/tables.c
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/drivers/uart/pl011.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/include/boot/coreboot_tables.h
M src/include/boot/tables.h
A src/include/boot/upl_fdt_table.h
M src/lib/Makefile.mk
M src/lib/bootmem.c
M src/lib/coreboot_table.c
A src/lib/tables.c
A src/lib/upl_fdt_table.c
M tests/lib/Makefile.mk
26 files changed, 649 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/76591/21
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Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84120?usp=email )
Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload
......................................................................
vc/google/chromeos: Skip boot info logging if cse sync at payload
This patch skips event logging for current boot information at ramstage
if CSE sync is scheduled at payload. Given that CSE sync could initiate
a system reset, resulting in redundant boot information logs, the
payload should handle the logging of boot information following CSE
sync.
BUG=b:360082747
TEST=Verified elog boot info is not logging at ramstage
Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/vendorcode/google/chromeos/elog.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/84120/1
diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c
index 4d3fc40..7e9e861 100644
--- a/src/vendorcode/google/chromeos/elog.c
+++ b/src/vendorcode/google/chromeos/elog.c
@@ -10,6 +10,13 @@
static void elog_add_vboot_info(void *unused)
{
+ /*
+ * Skip logging boot info if CSE sync scheduled at payload.
+ * The payload should log boot info after CSE sync.
+ */
+ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
+ return;
+
/* Skip logging boot info in ACPI resume path */
if (acpi_is_wakeup_s3())
return;
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Attention is currently required from: Arthur Heymans, Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Maximilian Brune, Philipp Hug, Simon Glass, ron minnich.
Hello Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Philipp Hug, Simon Glass, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#20).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: [RFC] Add UPL FDT handoff
......................................................................
[RFC] Add UPL FDT handoff
This adds another handoff that is basically the same as coreboot tables.
The only real difference is that it uses the devicetree format to
transfer the information to payload.
This handoff is inspired by the UPL (universal payload) specification.
Tested: start q35 qemu with coreinfo as payload and see that console
still works and the devicetree is printed by coreboot.
Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M payloads/Kconfig
M payloads/libpayload/arch/arm/coreboot.c
M payloads/libpayload/arch/arm64/coreboot.c
M payloads/libpayload/arch/x86/coreboot.c
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/Makefile.mk
A payloads/libpayload/libc/upl_fdt.c
M src/arch/arm/include/arch/cbconfig.h
M src/arch/arm64/include/arch/cbconfig.h
M src/arch/ppc64/include/arch/cbconfig.h
M src/arch/riscv/include/arch/cbconfig.h
M src/arch/x86/include/arch/cbconfig.h
M src/arch/x86/tables.c
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/drivers/uart/pl011.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/include/boot/coreboot_tables.h
M src/include/boot/tables.h
A src/include/boot/upl_fdt_table.h
M src/lib/Makefile.mk
M src/lib/bootmem.c
M src/lib/coreboot_table.c
A src/lib/tables.c
A src/lib/upl_fdt_table.c
M tests/lib/Makefile.mk
26 files changed, 649 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/76591/20
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Julius Werner has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/84087?usp=email )
Change subject: fit_payload: Use our region API
......................................................................
Patch Set 1: Code-Review+2
(2 comments)
Patchset:
PS1:
> Copying from CB:79907 so it's not forgotten: […]
Hmm... I think it's not that bad? Maybe we should add `region_move()` and `region_resize()` helpers that basically do the same thing to make this sort of stuff more readable?
I think we can consider this trusted because it's loading executable code that we're about to jump to anyway, yeah. When calling this from `payload_load()` (only entry point we have for now, I think), it comes from CBFS and is covered by verification if enabled.
File src/arch/riscv/fit_payload.c:
https://review.coreboot.org/c/coreboot/+/84087/comment/679817a7_ddbe2bd3?us… :
PS1, Line 98: region_offset(kernel) + region_sz(kernel)
Maybe we should still provide a `region_end()` helper (that's just `region_last() + 1`) for cases like this?
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Gerrit-Change-Number: 84087
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-Comment-Date: Wed, 28 Aug 2024 19:21:04 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>