coreboot-gerrit August 2024

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Ren Kuo (Code Review) 29 Aug '24

29 Aug '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email ) Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... mb/google/brox/jubilant: Update GPE0 routing Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/84124/1 diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 0613ff9..f337334 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -19,6 +19,12 @@ end chip soc/intel/alderlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + register "platform_pmax" = "208" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 @@ -448,7 +454,7 @@ register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" + register "wake" = "GPE0_DW1_15" register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[S] Change in blobs[main]: soc/intel/meteorlake: Add microcode for 06-b7-01
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has uploaded a new patch set (#4). ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/meteorlake: Add microcode for 06-b7-01 ...................................................................... soc/intel/meteorlake: Add microcode for 06-b7-01 The microcode and the redistribution license were published in a GitHub issue [1] from that repository. It might be added to the repository at some later point. The signature says: sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129 [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/… Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A soc/intel/meteorlake/06-b7-01 A soc/intel/meteorlake/LICENSE 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/22/84122/4 -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Tyler Wang (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Kenneth Chan, Nick Vaccaro, Ren Kuo. Tyler Wang has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84112?usp=email ) Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia1ad27786e0e3bd9c2110c8a28ab962c5567e16d Gerrit-Change-Number: 84112 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 02:08:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox/jubilant: update dptf settings
by Ren Kuo (Code Review) 29 Aug '24

29 Aug '24

Ren Kuo has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84123?usp=email ) Change subject: mb/google/brox/jubilant: update dptf settings ...................................................................... mb/google/brox/jubilant: update dptf settings Update dptf settings from thermal design: 1) Remove fan control and active policy, since fan is controlled by EC. 2) Modify TSRs to 0:DRAM, 1:SOC, 2:Charger 3) Update Pl2 min&max values BUG=None TEST= Build jubilant firmware Generate and check ACPI SSDT.dsl $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 17 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/84123/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Gerrit-Change-Number: 84123 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[S] Change in blobs[main]: soc/intel/meteorlake: Add microcode for 06-b7-01
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has uploaded a new patch set (#3). ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/meteorlake: Add microcode for 06-b7-01 ...................................................................... soc/intel/meteorlake: Add microcode for 06-b7-01 The microcode and the redistribution license were published in a GitHub issue [1] from that repository. It might be added to the repository add some later point. The signature says: sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129 [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/… Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A soc/intel/meteorlake/06-b7-01 A soc/intel/meteorlake/LICENSE 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/22/84122/3 -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: mb/google/brox/jubilant: update dptf settings
by Ren Kuo (Code Review) 29 Aug '24

29 Aug '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84123?usp=email ) Change subject: mb/google/brox/jubilant: update dptf settings ...................................................................... mb/google/brox/jubilant: update dptf settings Update dptf settings from thermal design: 1) Remvoe fan contorl and active policy, since fan is controlled by EC. 2) Modify TSRs to 0:DRAM, 1:SRC, 2:Charger 3) Update Pl2 min&max values BUG=None TEST= Build jubilant firmware Check ACPI SSDT table: $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT check SSDT.dsl hange-Id: I0043c728f1302e86c84849653f443dc560a51654 Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 17 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/84123/1 diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 0613ff9..6901213 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -45,51 +45,12 @@ register "options.tsr[1].desc" = ""Soc"" register "options.tsr[2].desc" = ""Charger"" - ## Active Policy - register "policies.active" = "{ - [0] = { - .target = DPTF_CPU, - .thresholds = { - TEMP_PCT(95, 90), - TEMP_PCT(92, 80), - TEMP_PCT(89, 60), - TEMP_PCT(85, 40), - TEMP_PCT(80, 30), - } - }, - [1] = { - .target = DPTF_TEMP_SENSOR_0, - .thresholds = { - TEMP_PCT(54, 95), - TEMP_PCT(52, 90), - TEMP_PCT(50, 80), - TEMP_PCT(48, 50), - TEMP_PCT(46, 30), - TEMP_PCT(44, 25), - TEMP_PCT(42, 20), - TEMP_PCT(40, 15), - } - }, - [2] = { - .target = DPTF_TEMP_SENSOR_1, - .thresholds = { - TEMP_PCT(54, 95), - TEMP_PCT(52, 90), - TEMP_PCT(50, 80), - TEMP_PCT(48, 50), - TEMP_PCT(46, 30), - TEMP_PCT(44, 25), - TEMP_PCT(42, 20), - TEMP_PCT(40, 15), - } - } - }" - ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000), }" ## Critical Policy @@ -97,23 +58,24 @@ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 18000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, - }, + .min_power = 15000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, .pl2 = { - .min_power = 55000, - .max_power = 55000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000, - } + .min_power = 41000, + .max_power = 41000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } }" ## Charger Performance Control (Control, mA) @@ -124,24 +86,6 @@ [3] = { 8, 500 } }" - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } - }" - - ## Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - device generic 0 alias dptf_policy on end end end # DTT -- To view, visit https://review.coreboot.org/c/coreboot/+/84123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Gerrit-Change-Number: 84123 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[S] Change in blobs[main]: soc/intel/meteorlake: Add microcode for 06-b7-01
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/meteorlake: Add microcode for 06-b7-01 ...................................................................... soc/intel/meteorlake: Add microcode for 06-b7-01 The microcode and the redistribution license were published in a GitHub issue [1] from that repository. It might be added to the repository add some later point. [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/… Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A soc/intel/meteorlake/06-b7-01 A soc/intel/meteorlake/LICENSE 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/22/84122/2 -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in blobs[main]: soc/intel/meteorlake: Add microcode for 06-b7-01
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/meteorlake: Add microcode for 06-b7-01 ...................................................................... soc/intel/meteorlake: Add microcode for 06-b7-01 The microcode and the redistribution license were published in a GitHub issue [1]. It might be added to the Git repository add some later point. [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/… Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A soc/intel/meteorlake/06-b7-01 A soc/intel/meteorlake/LICENSE 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/22/84122/1 diff --git a/soc/intel/meteorlake/06-b7-01 b/soc/intel/meteorlake/06-b7-01 new file mode 100644 index 0000000..ed73396 --- /dev/null +++ b/soc/intel/meteorlake/06-b7-01 Binary files differ diff --git a/soc/intel/meteorlake/LICENSE b/soc/intel/meteorlake/LICENSE new file mode 100644 index 0000000..cb763c9 --- /dev/null +++ b/soc/intel/meteorlake/LICENSE @@ -0,0 +1,37 @@ +Copyright (c) 2018-2021 Intel Corporation. +All rights reserved. + +Redistribution. + +Redistribution and use in binary form, without modification, are permitted, +provided that the following conditions are met: + +1. Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials provided + with the distribution. + +2. Neither the name of Intel Corporation nor the names of its suppliers may + be used to endorse or promote products derived from this software without + specific prior written permission. + +3. No reverse engineering, decompilation, or disassembly of this software + is permitted. + + +"Binary form" includes any format that is commonly used for electronic +conveyance that is a reversible, bit-exact translation of binary +representation to ASCII or ISO text, for example "uuencode". + +DISCLAIMER. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Enable VBOOT_DEFINE_WIDEVINE_COUNTERS
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84121?usp=email ) Change subject: soc/mediatek/mt8196: Enable VBOOT_DEFINE_WIDEVINE_COUNTERS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3760c30b175338165f8e11b59c7cfa830070a19e Gerrit-Change-Number: 84121 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 01:36:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox/jubilant: update dptf settings
by Ren Kuo (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Bob Moragues, Karthik Ramasubramanian, Kenneth Chan, Nick Vaccaro, Peter Ou. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84106?usp=email ) Change subject: mb/google/brox/jubilant: update dptf settings ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I see this in the EC code base. […] Yes. The Fan is controlled by EC. The thermal is passive policy on ACPI. -- To view, visit https://review.coreboot.org/c/coreboot/+/84106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0043c728f1302e86c84849653f443dc560a51654 Gerrit-Change-Number: 84106 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 01:31:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bob Moragues <moragues(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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coreboot-gerrit August 2024