Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/71585?usp=email )
Change subject: soc/intel/skylake/Makefile.inc: Remove path to non-existent directories
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/skylake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/71585/comment/06a4747f_5a8b1ab5?us… :
PS5, Line 112: ifeq ($(CONFIG_BOARD_STARLABS_STARBOOK_ADL) $(CONFIG_BOARD_STARLABS_LABTOP_CML) $(CONFIG_BOARD_STARLABS_STARBOOK_TGL) $(CONFIG_BOARD_OCP_TIOGAPASS),y)
> out scope and topic. […]
Heh? What's out of scope here? What is that supposed to tell me? You guarded that line with completely unrelated mainboards just to get rid of the error.
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Attention is currently required from: Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel.
Hello Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83719?usp=email
to look at the new patch set (#17).
Change subject: mb/lattepanda: Add support for LattePanda Mu
......................................................................
mb/lattepanda: Add support for LattePanda Mu
Add initial support for the LattePanda Mu board, which features:
- Intel Alder Lake-N N100 processor
- 8GB LPDDR5 memory
- 64GB eMMC storage
- SO-DIMM 260-pin connector for function expansion
This commit includes:
- Basic board configuration
- Memory initialization
- Essential I/O setup
- Used UEFITOOL to extract data.vbt file from original BIOS
Test Environment:
- Carrier Board: Lite
- Payload: mrchromebox/edk2
- Edk2 Version: uefipayload_202309
Test result
Passed:
- Windows 11 boot from eMMC
- Install Ubuntu 24.04 on NVMe SSD
- Ubuntu 24.04 boot from NVMe SSD
- USB 3.0/2.0 functionality
- HDMI output
- Realtek Ethernet
Known Issues:
- S3 sleep mode non-functional
- Power-on after shutdown requires power removal
- Windows 11 BSOD occurs with NVMe SSD installed
- SuperIO UART not detected in Windows 11
- NVMe SSD not working on Windows 11, except when:
- KDNet Debugging enabled on NIC during boot
- SSD becomes functional in this scenario
Change-Id: I79696bdd837a221860b32f54629212c3346dca66
Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com>
---
A configs/config.lattepanda_mu
A src/mainboard/lattepanda/Kconfig
A src/mainboard/lattepanda/Kconfig.name
A src/mainboard/lattepanda/mu/Kconfig
A src/mainboard/lattepanda/mu/Kconfig.name
A src/mainboard/lattepanda/mu/Makefile.mk
A src/mainboard/lattepanda/mu/board_info.txt
A src/mainboard/lattepanda/mu/bootblock.c
A src/mainboard/lattepanda/mu/data.vbt
A src/mainboard/lattepanda/mu/devicetree.cb
A src/mainboard/lattepanda/mu/dsdt.asl
A src/mainboard/lattepanda/mu/early_gpio.c
A src/mainboard/lattepanda/mu/gpio.c
A src/mainboard/lattepanda/mu/include/baseboard/gpio.h
A src/mainboard/lattepanda/mu/include/baseboard/variants.h
A src/mainboard/lattepanda/mu/mainboard.c
A src/mainboard/lattepanda/mu/memory.c
A src/mainboard/lattepanda/mu/ramstage.c
A src/mainboard/lattepanda/mu/romstage_fsp_params.c
A src/mainboard/lattepanda/mu/spd/Makefile.mk
A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex
A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex
22 files changed, 859 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/17
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Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/84120?usp=email )
Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84120/comment/9d1946ff_fd3cda5b?us… :
PS1, Line 16: logging
> logged?
Acknowledged
File src/vendorcode/google/chromeos/elog.c:
https://review.coreboot.org/c/coreboot/+/84120/comment/cd9f17d0_38aa01fd?us… :
PS1, Line 14:
> need one space more
Acknowledged
https://review.coreboot.org/c/coreboot/+/84120/comment/0d3273e5_bad30aa6?us… :
PS1, Line 13: /*
: * Skip logging boot info if CSE sync scheduled at payload.
: * The payload should log boot info after CSE sync.
: */
> Please align the comment asterisks correctly.
Acknowledged
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84120?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload
......................................................................
vc/google/chromeos: Skip boot info logging if cse sync at payload
This patch skips event logging for current boot information at ramstage
if CSE sync is scheduled at payload. Given that CSE sync could initiate
a system reset, resulting in redundant boot information logs, the
payload should handle the logging of boot information following CSE
sync.
BUG=b:360082747
TEST=Verified elog boot info is not logged at ramstage
Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/vendorcode/google/chromeos/elog.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/84120/2
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Change subject: mb/lattepanda: Add support for LattePanda Mu
......................................................................
Patch Set 15:
This change is ready for review.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/intel/meteorlake: Hook up microcode from repository
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84125/comment/f4e1c06b_78fd4164?us… :
PS4, Line 40: MICROCODE_BLOB_UNDISCLOSED
can i request you to use below code ?
```
select MICROCODE_BLOB_UNDISCLOSED if MAINBOARD_HAS_CHROMEOS
```
CrOS is not using public available ucode and Intel share the separate ucode to us which i assume is little ahead in timeline compared to the public available one. If you can still keep `MICROCODE_BLOB_UNDISCLOSED` for cros board, we don't need any special handling in downstream codebase.
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Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 5:
(3 comments)
File src/soc/intel/common/block/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/84103/comment/24b2272f_312d0643?us… :
PS5, Line 87: devices.
u should also mention that GPE1 Event Bit is an extension of GPE0 (present in all Intel SoC platform). Select this Kconfig for support SoCs that publishes GPE1 as part of PMC IO register.
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/84103/comment/58095ae5_e462c778?us… :
PS5, Line 29: GPE1_STS
this won't work. I believe you can use Kconfig over macro. that is more clean solution.
https://review.coreboot.org/c/coreboot/+/84103/comment/99ac1291_1c2743fa?us… :
PS5, Line 114: GPE1_STS(0)
```
CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1) ? (pmbase + GPE1_STS(0)) : 0
```
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Change subject: mb/lattepanda: Add support for LattePanda Mu
......................................................................
Patch Set 15:
This change is ready for review.
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 48:
(1 comment)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83789/comment/bef04a55_cdf096e4?us… :
PS17, Line 263: Since Lunarlake, OS pinctrl no long provides SOC GPIO pincntrl info.
: Rather, firmware is responsible for providing such info via APCI.
: Firmware can provide entire PADs or excluding those non GPP_[group]_[number]
: at the end of each community.
> Subrata,
>
> Can you also reference the changes on the kernel side?
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/d…
>
> thx
yes, i'm able to follow the changes
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