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Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek/mt8196: Add EINT support
......................................................................
soc/mediatek/mt8196: Add EINT support
BUG=b:334723688
TEST=EINT works in Rauru
Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/gpio_eint.c
2 files changed, 303 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84026/12
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Change subject: soc/intel/meteorlake: Hook up microcode from repository
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84125/comment/679574a3_fc8f016a?us… :
PS4, Line 40: MICROCODE_BLOB_UNDISCLOSED
> can i request you to use below code ? […]
Are you sure it makes a difference? It only changes the default.
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Change subject: soc/intel/meteorlake: Add microcode for 06-b7-01
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
Thanks! it's Raptor Lake, though
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Change subject: mb/lattepanda: Add support for LattePanda Mu
......................................................................
Patch Set 21:
(2 comments)
File src/mainboard/lattepanda/mu/bootblock.c:
https://review.coreboot.org/c/coreboot/+/83719/comment/45bf786d_b0e6565a?us… :
PS21, Line 20: /*
: * IT8613E Super I/O Chip Initialization Settings
: *
: * Source: IT8728FPeiInit module
: * Purpose: Configure the IT8613E Super I/O chip during system startup
: *
: * Analysis Process:
: * 1. Extract the 'IT8728FPeiInit' module from the original BIOS
: * using UEFITool NE alpha 68 (Nov 4 2023).
: * 2. Load the extracted module into Ghidra v11.1.2 for disassembly and analysis
: * 3. Identify and document the initialization settings from the disassembled code
: *
: */
Disassembling and reverse engineering are illegal in some jurisdictions. Better remove it.
https://review.coreboot.org/c/coreboot/+/83719/comment/4a80b06e_843baf6c?us… :
PS21, Line 96: static void it8613e_init(const u16 p_idx, const u16 p_dat, const struct initdata *table, const size_t count)
: {
: u8 val;
:
: for (size_t i = 0; i < count; i++) {
: outb(table[i].reg, p_idx);
:
: if (table[i].OpAnd == 0) {
: val = table[i].OpOr;
: } else {
: val = ((inb(p_dat) & table[i].OpAnd) |
: table[i].OpOr);
: }
:
: outb(val, p_dat);
: }
: }
Is it possible to do this in the Super I/O code (`src/superio/ite/it8613e/`)? This could be done later I guess.
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 8: Code-Review-2
(1 comment)
Patchset:
PS7:
> Subrata, Can google request Panther Lake Platform Firmware Architecture Specification (FAS), document # 812562? I don't see Google in the list of companies from our internal link.
I'm able to download PTL-FAS document. Any specific section you want me to pay attention ?
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Change subject: mb/google/brya: Add romstage early graphics for trulo baseboard
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
@amanda_hwang@compal.corp-partner.google.com: can you please this CL for Orisa and share your feedback. You should be able to see eSOL during boot like MRC or CSE update
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Change subject: mb/google/brya: Add romstage early graphics for trulo baseboard
......................................................................
mb/google/brya: Add romstage early graphics for trulo baseboard
1) Add all required changes for eSOL support.
2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo.
The CSOT (MNC207QS1-1) panel is used for the devicetree.
BUG=b:362895813
TEST=On-screen text message seen during MRC training on Trulo SKU1.
MRC: no data in 'RW_MRC_CACHE'
bootmode is set to: 0
DP PHY mode status not complete
DP PHY mode status not complete
DP PHY mode status not complete
...
Informing user on-display of memory training
Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
A src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads
4 files changed, 46 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/84128/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index f4c6f7c..b54b0db 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -113,6 +113,7 @@
select DRIVERS_AUDIO_SOF
select DRIVERS_INTEL_ISH
select MAINBOARD_DISABLE_STAGE_CACHE
+ select MAINBOARD_HAS_EARLY_LIBGFXINIT
select MEMORY_SOLDERDOWN
select SOC_INTEL_COMMON_MMC_OVERRIDE
select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
index be05cd4..cc62f1d 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
@@ -1,3 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
+romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads
romstage-y += memory.c
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index 5ce75c9..dc0d480 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -45,7 +45,37 @@
register "pch_hda_sdi_enable[1]" = "true"
device domain 0 on
- device ref igpu on end
+ # The timing values can be derived from datasheet of display panel
+ # You can use EDID string to identify the type of display on the board
+ # use below command to get display info from EDID
+ # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
+
+ # refer to display PRM document (Volume 2b: Command Reference: Registers)
+ # for more info on display control registers
+ # https://01.org/linuxgraphics/documentation/hardware-specification-prms
+ #+-----------------------------+---------------------------------------+-----+
+ #| Intel docs | devicetree.cb | eDP |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power up delay | `gpu_panel_power_up_delay` | T3 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power Down delay | `gpu_panel_power_down_delay` | T10 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
+ #+-----------------------------+---------------------------------------+-----+
+ device ref igpu on
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
+ end
device ref dtt on end
device ref tcss_xhci on end
device ref ish on
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads b/src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads
new file mode 100644
index 0000000..3b02f14
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads
@@ -0,0 +1,13 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+ ports : constant Port_List :=
+ (eDP,
+ others => Disabled);
+end GMA.Mainboard;
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS7:
> understood. I will bring this up and the chromebase case.
Subrata, Can google request Panther Lake Platform Firmware Architecture Specification (FAS), document # 812562? I don't see Google in the list of companies from our internal link.
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