coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

1 participants
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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Nicholas Chin, Nicholas Sudsgaard. Hello Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#19). Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - 8GB LPDDR5 memory - 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup - Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file from original BIOS - Download BIOS: https://github.com/LattePandaTeam/LattePanda-Mu under Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip Test Environment: - Carrier Board: Lite - Payload: mrchromebox/edk2 - Edk2 Version: uefipayload_202309 Test result Passed: - Windows 11 boot from eMMC - Install Ubuntu 24.04 on NVMe SSD - Ubuntu 24.04 boot from NVMe SSD - USB 3.0/2.0 functionality - HDMI output - Realtek Ethernet Known Issues: - S3 sleep mode non-functional - Power-on after shutdown requires power removal - Windows 11 BSOD occurs with NVMe SSD installed - SuperIO UART not detected in Windows 11 - NVMe SSD not working on Windows 11, except when: - KDNet Debugging enabled on NIC during boot - SSD becomes functional in this scenario Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/early_gpio.c A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 22 files changed, 861 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 19 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Paul Menzel (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Nicholas Chin, Nicholas Sudsgaard. Paul Menzel has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 18: Code-Review+1 (13 comments) Patchset: PS18: Great work! Commit Message: https://review.coreboot.org/c/coreboot/+/83719/comment/08c9a444_597f9ec3?us… : PS18, Line 11: 8GB LPDDR5 memory if you have the information, please note the vendor/model too. https://review.coreboot.org/c/coreboot/+/83719/comment/7e7c078c_0f2daffc?us… : PS18, Line 28: - Windows 11 boot from eMMC Also install? https://review.coreboot.org/c/coreboot/+/83719/comment/c9d6a761_3dc56be8?us… : PS18, Line 32: - HDMI output What about audio? Does it work over HDMI? https://review.coreboot.org/c/coreboot/+/83719/comment/df0f5009_be65f3e1?us… : PS18, Line 33: Realtek Ethernet Which is it? https://review.coreboot.org/c/coreboot/+/83719/comment/68d510f8_0fca103f?us… : PS18, Line 38: BSOD It’d be great if you mentioned the “id”/output of the BSOD. https://review.coreboot.org/c/coreboot/+/83719/comment/c5c82f13_14dc706a?us… : PS18, Line 43: Do you have some timeing numbers? Vendor firmware until boot loader and coreboot (with MRC cache) until boot loader? File src/mainboard/lattepanda/mu/bootblock.c: https://review.coreboot.org/c/coreboot/+/83719/comment/3978f939_bd509a6c?us… : PS18, Line 27: UEFITOOLS UEFITool https://review.coreboot.org/c/coreboot/+/83719/comment/a32d9b7b_896d2bd6?us… : PS18, Line 38: static const struct initdata it8613e_initdata[] Just one space after `initdata`. https://review.coreboot.org/c/coreboot/+/83719/comment/49a57df7_720077c6?us… : PS18, Line 64: initdata it8613e_ecdata[] Ditto. https://review.coreboot.org/c/coreboot/+/83719/comment/cb282b4e_87bea9be?us… : PS18, Line 95: u16 size_t? https://review.coreboot.org/c/coreboot/+/83719/comment/95610b00_366e9146?us… : PS18, Line 99: u16 `unsigned int` or `size_t` https://review.coreboot.org/c/coreboot/+/83719/comment/5bc61f9c_3d23abc6?us… : PS18, Line 102: if (table[i].OpAnd == 0) : val = table[i].OpOr; : else { : val = ((inb(p_dat) & table[i].OpAnd) | : table[i].OpOr); : } Please use curly brackets for both branches or no brackets. -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 18 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Aug 2024 05:44:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Paul Menzel (Code Review) 29 Aug '24

29 Aug '24

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[XS] Change in coreboot[main]: soc/intel/common/block/cpu: Fix ways count computation regression
by Paul Menzel (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Jérémy Compostella. Paul Menzel has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83948?usp=email ) Change subject: soc/intel/common/block/cpu: Fix ways count computation regression ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83948/comment/144f47e1_3c706e2c?us… : PS11, Line 32: TEST=Verified on PTL Intel reference platform For the ignorant, how can this be verified? -- To view, visit https://review.coreboot.org/c/coreboot/+/83948?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d Gerrit-Change-Number: 83948 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 05:32:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Use the effective way size for NEM+
by Paul Menzel (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Subrata Banik. Paul Menzel has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email ) Change subject: soc/intel/common/block/cpu: Use the effective way size for NEM+ ...................................................................... Patch Set 10: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83946/comment/2a0f37db_5d40a632?us… : PS10, Line 7: NEM+ This (with +) is not mentioned in the commit message body. https://review.coreboot.org/c/coreboot/+/83946/comment/e9e52f40_565f2c0d?us… : PS10, Line 7: Use the effective way size for NEM+ Maybe: > Add Kconfig for effective way size for NEM+ https://review.coreboot.org/c/coreboot/+/83946/comment/1fe5958a_7960373b?us… : PS10, Line 10: the : way size which should be considered for No-Eviction Mode (NEM) : purposes Add a comma at the end? https://review.coreboot.org/c/coreboot/+/83946/comment/e287ba26_b136337d?us… : PS10, Line 21: has been is https://review.coreboot.org/c/coreboot/+/83946/comment/ec29808f_c5e571e6?us… : PS10, Line 25: TEST=Verified on PTL Intel reference platform How? List the way size before and after? File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/83946/comment/9a8a1006_c420fb26?us… : PS10, Line 84: INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE I would misinterpret it, that platforms not selecting this use an *in*effective way size, but from your commit message that is not true as they use the MSR. `USE_POWER_OF_TWO_WAY_SIZE`? Or something with `NO_MSR` in it? https://review.coreboot.org/c/coreboot/+/83946/comment/10a99260_46043e42?us… : PS10, Line 87: On some platforms List the known ones? https://review.coreboot.org/c/coreboot/+/83946/comment/767603b7_aad831cd?us… : PS10, Line 87: the way size : which should be considered for eNEM purposes Add a comma at the end? -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 10 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 05:30:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Hello Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - 8GB LPDDR5 memory - 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup - Used UEFITOOL to extract data.vbt file from original BIOS Test Environment: - Carrier Board: Lite - Payload: mrchromebox/edk2 - Edk2 Version: uefipayload_202309 Test result Passed: - Windows 11 boot from eMMC - Install Ubuntu 24.04 on NVMe SSD - Ubuntu 24.04 boot from NVMe SSD - USB 3.0/2.0 functionality - HDMI output - Realtek Ethernet Known Issues: - S3 sleep mode non-functional - Power-on after shutdown requires power removal - Windows 11 BSOD occurs with NVMe SSD installed - SuperIO UART not detected in Windows 11 - NVMe SSD not working on Windows 11, except when: - KDNet Debugging enabled on NIC during boot - SSD becomes functional in this scenario Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/early_gpio.c A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 22 files changed, 861 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 18 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel: Use NEM+ effective way size for the right platforms
by Paul Menzel (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Subrata Banik, Tarun. Paul Menzel has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83947?usp=email ) Change subject: soc/intel: Use NEM+ effective way size for the right platforms ...................................................................... Patch Set 11: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83947/comment/5560d916_dea629ee?us… : PS11, Line 7: for the right platforms … for ADL, MTL, PTL https://review.coreboot.org/c/coreboot/+/83947/comment/23b9621f_c810bdb2?us… : PS11, Line 9: uses use https://review.coreboot.org/c/coreboot/+/83947/comment/fbae866d_c75d3853?us… : PS11, Line 11: Mode Fits on the line above? https://review.coreboot.org/c/coreboot/+/83947/comment/65d2c114_39bf0207?us… : PS11, Line 14: TEST=Verified on PTL Intel reference platform How? -- To view, visit https://review.coreboot.org/c/coreboot/+/83947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Gerrit-Change-Number: 83947 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 05:20:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 60: (1 comment) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/6748bcba_4f0c4135?us… : PS55, Line 247: (is_devfn_enabled(PCI_DEVFN_DPTF) || : is_devfn_enabled(PCI_DEVFN_IPU) || : is_devfn_enabled(PCI_DEVFN_NPU) || : is_devfn_enabled(PCI_DEVFN_IAA)) > why we need to check these logic twice? […] why we need to check these logic twice? one here and one at line#258-#265? > Hi Subrata, this check is introduced to check if none of the IPs (i.e., DPTF, IPU, NPU, IAA) are enabled, then it should create drhd table for nongfxvt. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 60 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 05:04:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel: Use NEM+ effective way size for the right platforms
by Sowmya Aralguppe (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83947?usp=email ) Change subject: soc/intel: Use NEM+ effective way size for the right platforms ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Gerrit-Change-Number: 83947 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 05:03:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: vc/google/chromeos: Skip boot info logging if cse sync at payload
by Subrata Banik (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Dinesh Gehlot, Paul Menzel. Subrata Banik has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/84120?usp=email ) Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50 Gerrit-Change-Number: 84120 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 04:55:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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