coreboot-gerrit August 2024

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[S] Change in blobs[main]: soc/intel/raptorlake: Add microcode for 06-b7-01
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/raptorlake: Add microcode for 06-b7-01 ...................................................................... soc/intel/raptorlake: Add microcode for 06-b7-01 The microcode and the redistribution license were published in a GitHub issue [1] from that repository. It might be added to the repository at some later point. The signature says: sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129 [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/… Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A soc/intel/raptorlake/06-b7-01 A soc/intel/raptorlake/LICENSE 2 files changed, 37 insertions(+), 0 deletions(-) Approvals: Nico Huber: Looks good to me, approved Felix Singer: Verified diff --git a/soc/intel/raptorlake/06-b7-01 b/soc/intel/raptorlake/06-b7-01 new file mode 100644 index 0000000..ed73396 --- /dev/null +++ b/soc/intel/raptorlake/06-b7-01 Binary files differ diff --git a/soc/intel/raptorlake/LICENSE b/soc/intel/raptorlake/LICENSE new file mode 100644 index 0000000..cb763c9 --- /dev/null +++ b/soc/intel/raptorlake/LICENSE @@ -0,0 +1,37 @@ +Copyright (c) 2018-2021 Intel Corporation. +All rights reserved. + +Redistribution. + +Redistribution and use in binary form, without modification, are permitted, +provided that the following conditions are met: + +1. Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials provided + with the distribution. + +2. Neither the name of Intel Corporation nor the names of its suppliers may + be used to endorse or promote products derived from this software without + specific prior written permission. + +3. No reverse engineering, decompilation, or disassembly of this software + is permitted. + + +"Binary form" includes any format that is commonly used for electronic +conveyance that is a reversible, bit-exact translation of binary +representation to ASCII or ISO text, for example "uuencode". + +DISCLAIMER. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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[S] Change in blobs[main]: soc/intel/raptorlake: Add microcode for 06-b7-01
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/raptorlake: Add microcode for 06-b7-01 ...................................................................... Patch Set 5: Verified+1 -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:09:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84117?usp=email ) Change subject: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84117/comment/ea8f24e4_151860ec?us… : PS2, Line 7: PCIE > PCIe Done https://review.coreboot.org/c/coreboot/+/84117/comment/07469ea9_1ed930b6?us… : PS2, Line 7: /common/pcie > Let's remove this to reduce the length. Done https://review.coreboot.org/c/coreboot/+/84117/comment/a4648533_b4dff687?us… : PS2, Line 10: 47 > 47ms Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:09:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84117?usp=email to look at the new patch set (#4). Change subject: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset ...................................................................... soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c 2 files changed, 54 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84117/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84118?usp=email to look at the new patch set (#4). Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... mb/google/cherry: Complete PCIe reset in romstage De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIE early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIE early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.mk 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/84118/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[S] Change in blobs[main]: soc/intel/raptorlake: Add microcode for 06-b7-01
by Nico Huber (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Felix Singer. Nico Huber has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/blobs/+/84122?usp=email ) Change subject: soc/intel/raptorlake: Add microcode for 06-b7-01 ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/84122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic274af7d862cf1c2fe0aaf8b9c228618fb970fad Gerrit-Change-Number: 84122 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:08:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#61). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,745 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/61 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 61 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XL] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Hello Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#25). Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory - Samsung KLMCG2UCTA-B041, 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup - Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file from original BIOS - BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu located at './"Softwares"/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip' Test Environment: - Carrier Board: Lite - Payload: mrchromebox/edk2 - EDK2 Version: uefipayload_202309 Test result Passed: - Windows 11 boot from eMMC - Install Ubuntu 24.04 on NVMe SSD - Ubuntu 24.04 boot from NVMe SSD - USB 3.0/2.0 functionality - Realtek RTL8111H-CG-RH Ethernet - HDMI Display - Audio over HDMI work in Ubuntu 24.04 Known Issues: - S3 sleep mode non-functional - Power-on after shutdown requires power removal - SuperIO UART not detected in Windows 11 - Audio over HDMI not work in Windows 11 - Windows 11 BSOD occurs with NVMe SSD installed: - Stop code: Machine Check Exception - NVMe SSD not working on Windows 11, except when: - KDNet Debugging enabled on NIC during boot - SSD becomes functional in this scenario Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A .tmpconfig.lintfl6486 A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/early_gpio.c A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/smihandler.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 24 files changed, 1,029 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 25 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up microcode from repository
by Nico Huber (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Nico Huber has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84125?usp=email ) Change subject: soc/intel/meteorlake: Hook up microcode from repository ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/84125/comment/2911029f_2d9d452e?us… : PS4, Line 40: MICROCODE_BLOB_UNDISCLOSED > > Are you sure it makes a difference? It only changes the default. […] Is the `cpu_microcode_bins` variable used with your configs? -- To view, visit https://review.coreboot.org/c/coreboot/+/84125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e Gerrit-Change-Number: 84125 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 09:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Felix Held, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. KunYi Chen has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 24: (2 comments) File src/mainboard/lattepanda/mu/bootblock.c: https://review.coreboot.org/c/coreboot/+/83719/comment/1934e83d_b03995b3?us… : PS21, Line 20: /* : * IT8613E Super I/O Chip Initialization Settings : * : * Source: IT8728FPeiInit module : * Purpose: Configure the IT8613E Super I/O chip during system startup : * : * Analysis Process: : * 1. Extract the 'IT8728FPeiInit' module from the original BIOS : * using UEFITool NE alpha 68 (Nov 4 2023). : * 2. Load the extracted module into Ghidra v11.1.2 for disassembly and analysis : * 3. Identify and document the initialization settings from the disassembled code : * : */ > Disassembling and reverse engineering are illegal in some jurisdictions. Better remove it. okay, remove the describe in latest patch https://review.coreboot.org/c/coreboot/+/83719/comment/8c933216_056c34c5?us… : PS21, Line 96: static void it8613e_init(const u16 p_idx, const u16 p_dat, const struct initdata *table, const size_t count) : { : u8 val; : : for (size_t i = 0; i < count; i++) { : outb(table[i].reg, p_idx); : : if (table[i].OpAnd == 0) { : val = table[i].OpOr; : } else { : val = ((inb(p_dat) & table[i].OpAnd) | : table[i].OpOr); : } : : outb(val, p_dat); : } : } > Is it possible to do this in the Super I/O code (`src/superio/ite/it8613e/`)? This could be done lat […] Due to the lack of a datasheet or programming guide for the IT8613E/LX, we need to explore alternative methods to address the power state transition issue on the board. -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 24 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Aug 2024 09:58:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit August 2024