coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

1 participants
3913 discussions

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 61: (1 comment) File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/1293e9d0_4510209d?us… : PS50, Line 143: disable_three_strike_error > Hi Subrata, we can take up this as a TODO. Currently can we proceed with PRE PRODUCTION SILICON change? i don't understand your statement. You should be able to check processor EDS and confirm if the 3-strike MSR is available for ESx silicon. If not then we need to introduce yet another Kconfig and use different means to handle the 3-strike between ESx and QSx silicon. Otherwords, are you seeing any issue if you just keep `disable_signaling_three_strike_event` API for early PTL SoC ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 61 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:51:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: amdfwtool: Set the field when the header is created
by Bao Zheng (Code Review) 29 Aug '24

29 Aug '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81729?usp=email ) Change subject: amdfwtool: Set the field when the header is created ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If363b4bc3f148c18432c9b2e0240554a62b51c68 Gerrit-Change-Number: 81729 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao

1 0

[S] Change in coreboot[main]: amdfwtool: Add a unified function to add combo entries
by Bao Zheng (Code Review) 29 Aug '24

29 Aug '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81728?usp=email ) Change subject: amdfwtool: Add a unified function to add combo entries ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib72d59341708acf4df84502b4973ec190b33aeb6 Gerrit-Change-Number: 81728 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao

1 0

[S] Change in coreboot[main]: amdfwtool: Set the field when the header is created
by Bao Zheng (Code Review) 29 Aug '24

29 Aug '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81727?usp=email ) Change subject: amdfwtool: Set the field when the header is created ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81727?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If363b4bc3f148c18432c9b2e0240554a62b51c68 Gerrit-Change-Number: 81727 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao

1 0

[S] Change in coreboot[main]: amdfwtool: Add a unified function to add combo entries
by Bao Zheng (Code Review) 29 Aug '24

29 Aug '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81734?usp=email ) Change subject: amdfwtool: Add a unified function to add combo entries ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib72d59341708acf4df84502b4973ec190b33aeb6 Gerrit-Change-Number: 81734 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 29 Aug '24

29 Aug '24

1 0

[XS] Change in coreboot[main]: 3rdparty/blobs: Update submodule to upstream main
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84129?usp=email ) Change subject: 3rdparty/blobs: Update submodule to upstream main ...................................................................... 3rdparty/blobs: Update submodule to upstream main Updating from commit id a8db7df: 2023-07-24 16:05:01 +0000 - (mb/google: amd projects: Add signed verstage files) to commit id 45f1b75: 2024-08-29 11:51:27 +0200 - (soc/intel/raptorlake: Add microcode for 06-b7-01) This brings in 7 new commits: 45f1b75 soc/intel/raptorlake: Add microcode for 06-b7-01 a0fdf22 soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1 c641a81 mb/erying/tgl: Add blobs necessary for platform bring-up 30e541a soc/mediatek/mt8192: Update dram.elf from 1.6.3 to 1.8.3 ba6e8a4 soc/intel: Remove Quark blobs 1f31acc soc/mediatek/mt8188: Update DRAM blob to 0.1.2 542c27d mb/starlabs/starbook: Consolidate version history Change-Id: I7553ea2112cb336866bdff3c24c02f8a7fd15811 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84129/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index a8db7df..45f1b75 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit a8db7dfe823def043368857b8fbfbba86f2e9e47 +Subproject commit 45f1b757402f9a0ae8a4e021a8f5745318515308 -- To view, visit https://review.coreboot.org/c/coreboot/+/84129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7553ea2112cb336866bdff3c24c02f8a7fd15811 Gerrit-Change-Number: 84129 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 61: (4 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/ff11ca3e_9afc7a17?us… : PS55, Line 238: 0x1 > are you checking BIT0? if yes, then what BIT-0 refers to here ? […] As per PTL FAS, which refers to LNL FAS #733648, section 11.5 1. VTd 0 Enabled (IOMMU 0 - gfx) Check Bit 0 set in (MCHBAR + 0x5410) 2. VTd 1 Enabled (IOMMU 1 – nongfx) Check Bit 1 set in (MCHBAR + 0x5410) 3. VTd Enabled (VTd 2 – Global IOMMU) Vtd Enabled in the platform if Bit 2 set in (MCHBAR + 0x5410) https://review.coreboot.org/c/coreboot/+/83798/comment/7d42c8f2_4a3b76a0?us… : PS55, Line 251: 0x2 > what is BIT(1)? need macro Acknowledged https://review.coreboot.org/c/coreboot/+/83798/comment/c5967cad_181e095d?us… : PS55, Line 330: 0x7 > what is this magic value ? can you please explain? As per PTL FAS, which refers to LNL FAS #733648, section 11.5 VTd 0 Enabled (IOMMU 0 - gfx) Check Bit 0 set in (MCHBAR + 0x5410) VTd 1 Enabled (IOMMU 1 – nongfx) Check Bit 1 set in (MCHBAR + 0x5410) VTd Enabled (VTd 2 – Global IOMMU) Vtd Enabled in the platform if Bit 2 set in (MCHBAR + 0x5410) So, here we are checking all the 3 bits to be enabled. Added (GFXVT_ENABLED | NONGFXVT_ENABLED | IOCVT_ENABLED) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/6b8949c9_21f64f06?us… : PS59, Line 272: 0x4 > No, not updated yet. Will make the change. I have added a new macro in https://review.coreboot.org/c/coreboot/+/83798/61/src/soc/intel/pantherlake… Updated to use these macros. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 61 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:14:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up microcode from repository
by Subrata Banik (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Nico Huber, Tarun. Subrata Banik has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84125?usp=email ) Change subject: soc/intel/meteorlake: Hook up microcode from repository ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/84125/comment/387656ad_4bbc1e57?us… : PS4, Line 40: MICROCODE_BLOB_UNDISCLOSED > Is the `cpu_microcode_bins` variable used with your configs? I'm marking this as resolved because we're using `CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS` for MTL, which means we won't be falling back to the path that this CL was intended to address. So there should be no impact on our side. -- To view, visit https://review.coreboot.org/c/coreboot/+/84125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e Gerrit-Change-Number: 84125 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:11:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84118?usp=email ) Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84118/comment/d1e00c00_4fe04496?us… : PS2, Line 7: PCIE > PCIe Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 10:09:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2024