coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84115?usp=email ) Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/84115/comment/287722e3_9a384e8a?us… : PS2, Line 250: base > `reg` or `base_reg` or `reg_base`. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Gerrit-Change-Number: 84115 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 12:39:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: [RFC] Add UPL FDT handoff
by Maximilian Brune (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Arthur Heymans, Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Philipp Hug, Simon Glass, ron minnich. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/76591?usp=email ) Change subject: [RFC] Add UPL FDT handoff ...................................................................... Patch Set 21: (1 comment) File payloads/libpayload/arch/arm/coreboot.c: https://review.coreboot.org/c/coreboot/+/76591/comment/51687e6c_5b618cc5?us… : PS17, Line 60: if (CONFIG(LP_UPL)) > Done Jenkins just made me realize that we cannot do that in runtime, because UPL is GPL licensed code (through `commonlib/device_tree`) and if I always built in both coreboot table and UPL parser we wouldn't be able to create payloads anymore that are fully BSD. -- To view, visit https://review.coreboot.org/c/coreboot/+/76591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Gerrit-Change-Number: 76591 Gerrit-PatchSet: 21 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 12:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yu-Ping Wu. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84117?usp=email to look at the new patch set (#6). Change subject: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset ...................................................................... soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c 2 files changed, 54 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84117/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yu-Ping Wu. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84118?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... mb/google/cherry: Complete PCIe reset in romstage De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.mk 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/84118/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[XS] Change in coreboot[main]: Update fsp submodule to upstream main
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84111?usp=email ) Change subject: Update fsp submodule to upstream main ...................................................................... Update fsp submodule to upstream main Updating from commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) to commit id 68328e2: 2024-08-05 16:00:43 +0800 - (NEX ADL-PS IPU 2024.4 (5045_03) FSP) This brings in 10 new commits: * NEX ADL-PS IPU 2024.4 (5045_03) FSP * NEX ADL-P IPU 2024.4 (5045_03) FSP * NEX ADL-S IPU 2024.4 (5045_03) FSP * IoT MTL-UH_MTL-PS MR1 (4053_57) FSP * NEX RPL-S MR4/RPL-S Refresh MR2 (5134_02) FSP * NEX RPL-P MR2 (5134_02) FSP * NEX ADL-P IPU 2024.3 (5045_02) FSP * NEX MTL-UH & MTL-PS Post PV * Iot ADL-N MR5 (5132_00) * remove file Change-Id: Ief40f675556bce662601d7d8db6660f72dc35961 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84111 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/fsp b/3rdparty/fsp index 800c857..68328e2 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 800c85770b458ee7f7eeb1276b46e904590d3bd7 +Subproject commit 68328e297e195a6cfb1949b60d971c032a172ba3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief40f675556bce662601d7d8db6660f72dc35961 Gerrit-Change-Number: 84111 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Update intel-microcode submodule to upstream main
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84110?usp=email ) Change subject: Update intel-microcode submodule to upstream main ...................................................................... Update intel-microcode submodule to upstream main Updating from commit id 5278dfc: 2024-05-31 18:42:47 -0600 - (microcode-20240531 Release) to commit id 2f56505: 2024-08-14 19:59:27 -0600 - (microcode-20240813 Release) This brings in 1 new commits: 2f56505 microcode-20240813 Release Change-Id: I5cf5d78bcda07f742a8282b84a1c8336e6a23594 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84110 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 5278dfc..2f56505 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 5278dfcf98e89098326b3eb8a85d07120a8730f8 +Subproject commit 2f5650548f37a6fb195e9e423389537a87ac95df -- To view, visit https://review.coreboot.org/c/coreboot/+/84110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cf5d78bcda07f742a8282b84a1c8336e6a23594 Gerrit-Change-Number: 84110 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84115?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ...................................................................... soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8195/include/soc/pcie.h M src/soc/mediatek/mt8195/pcie.c 5 files changed, 15 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84115/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Gerrit-Change-Number: 84115 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset
by Yidi Lin (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yu-Ping Wu. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84117?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset ...................................................................... soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c 2 files changed, 54 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84117/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[XS] Change in coreboot[main]: util/hda-decoder: Protect 'fields' slice if empty string
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84101?usp=email ) Change subject: util/hda-decoder: Protect 'fields' slice if empty string ...................................................................... util/hda-decoder: Protect 'fields' slice if empty string This avoids panic if the file contains an empty string or an incorrect configuration: goroutine 1 [running]: main.decodeFile({0x7ffd63da92a0?, 0xc000014070?}, 0x8?) /path/to/coreboot/util/hda-decoder/main.go:72 +0x2ef main.main() /path/to/coreboot/util/hda-decoder/main.go:158 +0x2a5 Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84101 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/hda-decoder/main.go 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/hda-decoder/main.go b/util/hda-decoder/main.go index 83ddcbb..d686f19 100644 --- a/util/hda-decoder/main.go +++ b/util/hda-decoder/main.go @@ -69,6 +69,11 @@ for scanner.Scan() { fields := strings.Fields(scanner.Text()) + if len(fields) != 2 { + fmt.Print("// Something went wrong\n") + continue + } + pin := stringToUint32(fields[0]) config := stringToUint32(fields[1]) -- To view, visit https://review.coreboot.org/c/coreboot/+/84101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Gerrit-Change-Number: 84101 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/nova: Configure scaler I2C GPIOs
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84091?usp=email ) Change subject: mb/google/brya/var/nova: Configure scaler I2C GPIOs ...................................................................... mb/google/brya/var/nova: Configure scaler I2C GPIOs According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL). BUG=b:358439747 TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C. Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091 Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/variants/nova/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified David Wu: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nova/gpio.c b/src/mainboard/google/brya/variants/nova/gpio.c index e895244..ce4d11d 100644 --- a/src/mainboard/google/brya/variants/nova/gpio.c +++ b/src/mainboard/google/brya/variants/nova/gpio.c @@ -91,6 +91,10 @@ /* F16 : GSXCLK ==> MEM_STRAP_0 */ PAD_CFG_GPI_LOCK(GPP_F16, NONE, LOCK_CONFIG), + /* H4 : I2C0_SDA ==> PCH_I2C_SCALER_SDA */ + PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG), + /* H5 : I2C0_SCL ==> PCH_I2C_SCALER_SCL */ + PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG), /* H12 : I2C7_SDA ==> NC */ PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b Gerrit-Change-Number: 84091 Gerrit-PatchSet: 5 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit August 2024