coreboot-gerrit August 2024

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[S] Change in libgfxinit[main]: gma display_probing: Make new TGL ports available
by Angel Pons (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Nico Huber, Paul Menzel, Thomas Heijligen. Angel Pons has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/libgfxinit/+/81522?usp=email ) Change subject: gma display_probing: Make new TGL ports available ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File common/hw-gfx-gma-display_probing.adb: https://review.coreboot.org/c/libgfxinit/+/81522/comment/8dd1e130_cf6e7531?… : PS7, Line 38: function Sibling_Port (Port : Port_Type) return Port_Type is > Isn't USBCx_DP = USBCx_HDMI now? Yes, but DPx and HDMIx refer to the traditional (not Type-C capable) ports. I think this is fine. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/81522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I9d96673f931be0086536044694ecd127ba2a823d Gerrit-Change-Number: 81522 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 29 Aug 2024 15:32:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de>

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[M] Change in coreboot[main]: arch/riscv: Refactor SMP code
by Maximilian Brune (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Philipp Hug, Tim Wawrzynczak, ron minnich. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81082?usp=email ) Change subject: arch/riscv: Refactor SMP code ...................................................................... Patch Set 5: (2 comments) File src/arch/riscv/smp.c: https://review.coreboot.org/c/coreboot/+/81082/comment/cc29ca5d_d98d57aa?us… : PS5, Line 49: for (int i = 0; i < hart_count; i++) { > There seems to be an assumption that hartid are always contiguous from 0, is that the case? good point. It is the case for all platforms I have encountered so far, but it is not mandated by the RISC-V spec. There are currently multiple places where we assume continues hart ids. `OTHER_HLS` macros and friends and our stack setup (at least partly). I guess at some point there will be a special snowflake SOC that doesn't have continuous hart ids. For this patch I would keep the assumption (since the assumption was present also before this patch). I would propose to do a separate patch that removes the assumption from the entire `arch/riscv` codebase. https://review.coreboot.org/c/coreboot/+/81082/comment/fa71d59e_b6da3f62?us… : PS5, Line 80: while (atomic_read(&OTHER_HLS(i)->entry.sync_a) != 0) > should there be a timeout ? I currently assume the time between `smp_pause` and `smp_resume` is enough for a timeout right now. But I can also add a timeout if you want. -- To view, visit https://review.coreboot.org/c/coreboot/+/81082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587 Gerrit-Change-Number: 81082 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 15:28:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/raptorlake: Use updated microcode from blobs repo
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84132?usp=email ) Change subject: soc/intel/raptorlake: Use updated microcode from blobs repo ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Submitted early since several people are asking for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/84132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Gerrit-Change-Number: 84132 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 14:43:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: 3rdparty/blobs: Update submodule to upstream main
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84129?usp=email ) Change subject: 3rdparty/blobs: Update submodule to upstream main ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Submitted early since several people are asking for the microcode update (45f1b75). -- To view, visit https://review.coreboot.org/c/coreboot/+/84129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7553ea2112cb336866bdff3c24c02f8a7fd15811 Gerrit-Change-Number: 84129 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 14:42:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/raptorlake: Use updated microcode from blobs repo
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84132?usp=email ) Change subject: soc/intel/raptorlake: Use updated microcode from blobs repo ...................................................................... soc/intel/raptorlake: Use updated microcode from blobs repo This updated microcode fixes the recent voltage issues on the Raptor Lake S platform. Intel provided this specific microcode just as an attachment [1]. Thus, we've uploaded it to our own blobs repository, which is why the path is changed. Microcode signature: sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129 [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/… Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84132 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 55fc83ea..2246c86 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -82,7 +82,7 @@ # ADL-S/HX C0/H0 and RPL-S C0/H0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 # RPL-S/HX B0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 +cpu_microcode_bins += 3rdparty/blobs/soc/intel/raptorlake/06-b7-01 else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00 else -- To view, visit https://review.coreboot.org/c/coreboot/+/84132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Gerrit-Change-Number: 84132 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: 3rdparty/blobs: Update submodule to upstream main
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84129?usp=email ) Change subject: 3rdparty/blobs: Update submodule to upstream main ...................................................................... 3rdparty/blobs: Update submodule to upstream main Updating from commit id a8db7df: 2023-07-24 16:05:01 +0000 - (mb/google: amd projects: Add signed verstage files) to commit id 45f1b75: 2024-08-29 11:51:27 +0200 - (soc/intel/raptorlake: Add microcode for 06-b7-01) This brings in 7 new commits: 45f1b75 soc/intel/raptorlake: Add microcode for 06-b7-01 a0fdf22 soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1 c641a81 mb/erying/tgl: Add blobs necessary for platform bring-up 30e541a soc/mediatek/mt8192: Update dram.elf from 1.6.3 to 1.8.3 ba6e8a4 soc/intel: Remove Quark blobs 1f31acc soc/mediatek/mt8188: Update DRAM blob to 0.1.2 542c27d mb/starlabs/starbook: Consolidate version history Change-Id: I7553ea2112cb336866bdff3c24c02f8a7fd15811 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84129 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/blobs b/3rdparty/blobs index a8db7df..45f1b75 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit a8db7dfe823def043368857b8fbfbba86f2e9e47 +Subproject commit 45f1b757402f9a0ae8a4e021a8f5745318515308 -- To view, visit https://review.coreboot.org/c/coreboot/+/84129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7553ea2112cb336866bdff3c24c02f8a7fd15811 Gerrit-Change-Number: 84129 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in libgfxinit[main]: gma display_probing: Make new TGL ports available
by Thomas Heijligen (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Nico Huber, Paul Menzel. Thomas Heijligen has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/libgfxinit/+/81522?usp=email ) Change subject: gma display_probing: Make new TGL ports available ...................................................................... Patch Set 7: (1 comment) File common/hw-gfx-gma-display_probing.adb: https://review.coreboot.org/c/libgfxinit/+/81522/comment/97762e0f_b33716d7?… : PS7, Line 38: function Sibling_Port (Port : Port_Type) return Port_Type is Isn't USBCx_DP = USBCx_HDMI now? -- To view, visit https://review.coreboot.org/c/libgfxinit/+/81522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I9d96673f931be0086536044694ecd127ba2a823d Gerrit-Change-Number: 81522 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 29 Aug 2024 14:11:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/raptorlake: Use updated microcode from blobs repo
by Nico Huber (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Dinesh Gehlot, Felix Singer, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik. Nico Huber has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84132?usp=email ) Change subject: soc/intel/raptorlake: Use updated microcode from blobs repo ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Gerrit-Change-Number: 84132 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 14:05:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: cbmem.h: Change return type of cbmem_get_region
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84039?usp=email ) Change subject: cbmem.h: Change return type of cbmem_get_region ...................................................................... cbmem.h: Change return type of cbmem_get_region The underlying IMD function already returns an integer which indicates success or failure. This removes the need to have initialized variables that need to be checked for NULL later. In some cases this actually adds the appropriate check for returned values. Dying is appropriate if cbmem is not found as it is essential to the bootflow. Change-Id: Ib3e09a75380faf9f533601368993261f042422ef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84039 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/postcar_loader.c M src/include/cbmem.h M src/lib/fit_payload.c M src/lib/imd_cbmem.c M src/security/memory/memory_clear.c M src/soc/intel/xeon_sp/memmap.c M tests/lib/Makefile.mk 7 files changed, 23 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 2d7bb48..aac4af8 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -147,7 +147,8 @@ uintptr_t stage_cache_base; size_t stage_cache_size; - cbmem_get_region((void **)&cbmem_base, &cbmem_size); + if (cbmem_get_region((void **)&cbmem_base, &cbmem_size)) + die("Could not find cbmem region"); prog_segment_loaded(cbmem_base, cbmem_size, SEG_FINAL); if (CONFIG(TSEG_STAGE_CACHE) && !romstage_handoff_is_resume()) { stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index de305ae..fd258cd 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -102,7 +102,7 @@ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); /* Return the cbmem memory used */ -void cbmem_get_region(void **baseptr, size_t *size); +int cbmem_get_region(void **baseptr, size_t *size); void cbmem_list(void); void cbmem_add_records_to_cbtable(struct lb_header *header); diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 21bc4e8..aea1ba7 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -110,8 +110,8 @@ { u32 addr_cells = 1, size_cells = 1; u64 reg_addrs[2], reg_sizes[2]; - void *baseptr = NULL; - size_t size = 0; + void *baseptr; + size_t size; static const char *firmware_path[] = {"firmware", NULL}; struct device_tree_node *firmware_node = dt_find_node(tree->root, @@ -140,8 +140,7 @@ /* Second is the CBMEM area (which usually includes the coreboot table). */ - cbmem_get_region(&baseptr, &size); - if (!baseptr || size == 0) { + if (cbmem_get_region(&baseptr, &size)) { printk(BIOS_WARNING, "FIT: CBMEM pointer/size not found!\n"); return; } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index a88cf98..2fc54bf 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -193,16 +193,19 @@ void cbmem_add_bootmem(void) { - void *baseptr = NULL; - size_t size = 0; + void *baseptr; + size_t size; - cbmem_get_region(&baseptr, &size); + if (cbmem_get_region(&baseptr, &size)) { + printk(BIOS_ERR, "CBMEM pointer/size not found!\n"); + return; + } bootmem_add_range((uintptr_t)baseptr, size, BM_MEM_TABLE); } -void cbmem_get_region(void **baseptr, size_t *size) +int cbmem_get_region(void **baseptr, size_t *size) { - imd_region_used(&imd, baseptr, size); + return imd_region_used(&imd, baseptr, size); } #if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) && ENV_HAS_CBMEM) diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 9af3205..9a8a23a 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -74,12 +74,13 @@ BM_MEM_RAM); /* Add reserved entries */ - void *baseptr = NULL; - size_t size = 0; + void *baseptr; + size_t size; /* Only skip CBMEM, stage program, stack and heap are included there. */ - cbmem_get_region(&baseptr, &size); + if (cbmem_get_region(&baseptr, &size)) + die("Could not find cbmem region"); memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE); if (ENV_X86) { diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index bf4c13e..b70c1cc 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -35,7 +35,8 @@ size_t cbmem_size; /* Try account for the CBMEM region currently used and for future use */ - cbmem_get_region((void **)&cbmem_base, &cbmem_size); + if (cbmem_get_region((void **)&cbmem_base, &cbmem_size)) + die("Could not find cbmem region"); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size); /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ diff --git a/tests/lib/Makefile.mk b/tests/lib/Makefile.mk index 7fc5471..1a96c7d 100644 --- a/tests/lib/Makefile.mk +++ b/tests/lib/Makefile.mk @@ -55,6 +55,7 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c imd-test-srcs += src/lib/imd.c +imd-test-srcs += tests/stubs/die.c timestamp-test-srcs += tests/lib/timestamp-test.c timestamp-test-srcs += tests/stubs/timestamp.c @@ -85,12 +86,14 @@ imd_cbmem-ramstage-test-srcs += tests/stubs/console.c imd_cbmem-ramstage-test-srcs += src/lib/imd.c imd_cbmem-ramstage-test-mocks += cbmem_top_chipset +imd_cbmem-ramstage-test-srcs += tests/stubs/die.c imd_cbmem-romstage-test-stage := romstage imd_cbmem-romstage-test-srcs += tests/lib/imd_cbmem-test.c imd_cbmem-romstage-test-srcs += tests/stubs/console.c imd_cbmem-romstage-test-srcs += src/lib/imd.c imd_cbmem-romstage-test-mocks += cbmem_top_chipset +imd_cbmem-romstage-test-srcs += tests/stubs/die.c region_file-test-srcs += tests/lib/region_file-test.c region_file-test-srcs += src/commonlib/region.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3e09a75380faf9f533601368993261f042422ef Gerrit-Change-Number: 84039 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: lib/rmodules: Add support for LTO
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84038?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: lib/rmodules: Add support for LTO ...................................................................... lib/rmodules: Add support for LTO Change-Id: I9cdda036f330486370e8c4120be5b6a0fd982e99 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84038 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/lib/Makefile.mk 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk index 89e5b65..40df2b8 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk @@ -314,7 +314,11 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(3)) $(call src-to-obj,rmodules_$(3),src/lib/rmodule.ld) | $$(RMODTOOL) +ifeq ($(CONFIG_LTO),y) + $$(CC_rmodules_$(3)) $$(CPPFLAGS_rmodules_$(3)) $$(CFLAGS_rmodules_$(3)) $$(LDFLAGS_rmodules_$(3):%=-Wl,%) $$(COMPILER_RT_FLAGS_rmodules_$(3):%=-Wl,%) $(RMODULE_LDFLAGS) $($(1)-ldflags:%=-Wl,%) -T $(call src-to-obj,rmodules_$(3),src/lib/rmodule.ld) -o $$@ -Wl,--whole-archive -Wl,--start-group $(filter-out %.ld,$(2)) -Wl,--no-whole-archive $$(COMPILER_RT_rmodules_$(3)) -Wl,--end-group +else $$(LD_rmodules_$(3)) $$(LDFLAGS_rmodules_$(3)) $(RMODULE_LDFLAGS) $($(1)-ldflags) -T $(call src-to-obj,rmodules_$(3),src/lib/rmodule.ld) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --no-whole-archive $$(COMPILER_RT_rmodules_$(3)) --end-group +endif $$(NM_rmodules_$(3)) -n $$@ > $$(basename $$(a)).map endef -- To view, visit https://review.coreboot.org/c/coreboot/+/84038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cdda036f330486370e8c4120be5b6a0fd982e99 Gerrit-Change-Number: 84038 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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