coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

1 participants
3913 discussions

[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 5: (6 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/64ef8a3f_23e44e2d?us… : PS5, Line 29: GPE1_STS > sure. will make the change. can you please use my git diff ``` git diff diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 25854837faf..84b8467070b 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -26,9 +26,10 @@ #define CPUID_6_EAX_ISST (1 << 7) #define ACPI_SCI_IRQ 9 -#ifndef GPE1_STS +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1) /* NOTE: For platform doesn't have support for GPE1, adding dummy entry here for common code */ -#define GPE1_STS(x) (0x0 + ((x) * 4)) +#define GPE1_STS(x) (0x0 + ((x) * 4)) +#define GPE1_REG_MAX 0 #endif void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) @@ -112,7 +113,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : GPE1_STS(0); - if (!fadt->gpe1_blk) { + if (fadt->gpe1_blk) { fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t); /* * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets. ``` https://review.coreboot.org/c/coreboot/+/84103/comment/49b1c7a5_5e5b01c6?us… : PS5, Line 31: just use one space https://review.coreboot.org/c/coreboot/+/84103/comment/b421e148_e0e364af?us… : PS5, Line 31: drop one space https://review.coreboot.org/c/coreboot/+/84103/comment/27afe9c2_9d9fa368?us… : PS5, Line 114: one space https://review.coreboot.org/c/coreboot/+/84103/comment/60cb67e7_fb23541d?us… : PS5, Line 115: !fadt->gpe1_blk we wish to program gpe1_blk_len if gpe1_blk is not zero. ``` if (fadt->gpe1_blk) { ``` https://review.coreboot.org/c/coreboot/+/84103/comment/fd793e7f_bd04a900?us… : PS5, Line 116: GPE1_REG_MAX not defined -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 13:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: cpu/x86/smm: Don't do partial linking
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84037?usp=email ) Change subject: cpu/x86/smm: Don't do partial linking ...................................................................... cpu/x86/smm: Don't do partial linking For LTO we want to link everything in one go. Change-Id: If2c186eb87072e0b80c7e8998b2a0d9bdfddf740 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84037 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/smm/Makefile.mk M src/lib/Makefile.mk 2 files changed, 7 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/cpu/x86/smm/Makefile.mk b/src/cpu/x86/smm/Makefile.mk index 33b24a8..a104a87 100644 --- a/src/cpu/x86/smm/Makefile.mk +++ b/src/cpu/x86/smm/Makefile.mk @@ -17,8 +17,10 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps+=$$(OPTION_TABLE_H) -$(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group +$(obj)/smm/smm.a: $$(smm-objs) + $(AR_smm) rcsT $@.tmp $(filter-out %.ld, $(smm-objs)) + mv $@.tmp $@ + # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -65,9 +67,9 @@ # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o,x86_32)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a,x86_32)) else -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o,x86_64)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a,x86_64)) endif $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk index 56d8b1a..89e5b65 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk @@ -314,7 +314,7 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(3)) $(call src-to-obj,rmodules_$(3),src/lib/rmodule.ld) | $$(RMODTOOL) - $$(LD_rmodules_$(3)) $$(LDFLAGS_rmodules_$(3)) $(RMODULE_LDFLAGS) $($(1)-ldflags) -T $(call src-to-obj,rmodules_$(3),src/lib/rmodule.ld) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(3)) $$(LDFLAGS_rmodules_$(3)) $(RMODULE_LDFLAGS) $($(1)-ldflags) -T $(call src-to-obj,rmodules_$(3),src/lib/rmodule.ld) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --no-whole-archive $$(COMPILER_RT_rmodules_$(3)) --end-group $$(NM_rmodules_$(3)) -n $$@ > $$(basename $$(a)).map endef -- To view, visit https://review.coreboot.org/c/coreboot/+/84037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If2c186eb87072e0b80c7e8998b2a0d9bdfddf740 Gerrit-Change-Number: 84037 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: cpu/x86/64bit: Specify linker to be used for cbfs PT
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84057?usp=email ) Change subject: cpu/x86/64bit: Specify linker to be used for cbfs PT ...................................................................... cpu/x86/64bit: Specify linker to be used for cbfs PT When clang supports linking bare metal targets it defaults to LLD for linking which linking those raw data structures used to generate CBFS page tables does not fare well. Change-Id: I66fb374a456ea752a97a41426c5a98e6747f3a92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84057 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/x86/64bit/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk index 1fda087..8ce3665 100644 --- a/src/cpu/x86/64bit/Makefile.mk +++ b/src/cpu/x86/64bit/Makefile.mk @@ -13,7 +13,7 @@ # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/$(PAGETABLE_SRC) $(obj)/config.h - $(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -o $@.tmp $< -Wl,--section-start=.rodata=$(CONFIG_ARCH_X86_64_PGTBL_LOC),--defsym=_start=0 + $(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -o $@.tmp $< -Wl,--section-start=.rodata=$(CONFIG_ARCH_X86_64_PGTBL_LOC),--defsym=_start=0 -fuse-ld=bfd $(OBJCOPY_ramstage) -Obinary -j .rodata $@.tmp $@ rm $@.tmp -- To view, visit https://review.coreboot.org/c/coreboot/+/84057?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66fb374a456ea752a97a41426c5a98e6747f3a92 Gerrit-Change-Number: 84057 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/rauru: Reset USB hub in bootblock
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84024?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Reset USB hub in bootblock ...................................................................... mb/google/rauru: Reset USB hub in bootblock We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. TEST=build pass. BUG=b:317009620 Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/bootblock.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index a896b72..578ec75 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -3,7 +3,15 @@ #include <bootblock_common.h> #include <soc/spi.h> +#include "gpio.h" + +static void usb3_hub_reset(void) +{ + gpio_output(GPIO(USB_RST), 1); +} + void bootblock_mainboard_init(void) { mtk_snfc_init(); + usb3_hub_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84024?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Gerrit-Change-Number: 84024 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com>

1 0

[XS] Change in coreboot[main]: mb/google/rauru: Setup USB host in ramstage
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84022?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Setup USB host in ramstage ...................................................................... mb/google/rauru: Setup USB host in ramstage Add usb host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/mainboard.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index af12d21..195ce67 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/usb.h> static void mainboard_init(struct device *dev) { - /* TODO: add mainboard init */ + setup_usb_host(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/84022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5 Gerrit-Change-Number: 84022 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Add USB host support
by Felix Held (Code Review) 29 Aug '24

29 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84023?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add USB host support ...................................................................... soc/mediatek/mt8196: Add USB host support Add USB host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Change-Id: Ia4efcddac9bf5e04e688648a5c22384075a0b026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/usb.h A src/soc/mediatek/mt8196/usb.c 3 files changed, 50 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 37326df..c8845ac 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -22,6 +22,7 @@ ramstage-y += l2c_ops.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += soc.c +ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8196/include/soc/usb.h b/src/soc/mediatek/mt8196/include/soc/usb.h new file mode 100644 index 0000000..5733da2 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/usb.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 5.5 + */ + +#ifndef SOC_MEDIATEK_MT8196_USB_H +#define SOC_MEDIATEK_MT8196_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64 * 5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 1 + +#endif diff --git a/src/soc/mediatek/mt8196/usb.c b/src/soc/mediatek/mt8196/usb.c new file mode 100644 index 0000000..56fe15c --- /dev/null +++ b/src/soc/mediatek/mt8196/usb.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 13.1,13.2 + */ + +#include <soc/addressmap.h> +#include <device/mmio.h> +#include <soc/usb.h> + +#define CTRL_U3_PORT_SS_SUP_SPEED (3U << 9) + +void mtk_usb_prepare(void) +{ + /* SW sets this register to change USB3.2 speed to Gen1-5Gbps */ + struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE); + + clrsetbits32(&ippc_regs->u3_ctrl_p[0], CTRL_U3_PORT_SS_SUP_SPEED, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4efcddac9bf5e04e688648a5c22384075a0b026 Gerrit-Change-Number: 84023 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/raptorlake: Use updated microcode from blobs repo
by Felix Singer (Code Review) 29 Aug '24

29 Aug '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84132?usp=email ) Change subject: soc/intel/raptorlake: Use updated microcode from blobs repo ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Gerrit-Change-Number: 84132 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 13:22:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yu-Ping Wu (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84118?usp=email ) Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 12:52:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset
by Yu-Ping Wu (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84117?usp=email ) Change subject: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 12:51:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
by Yu-Ping Wu (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84115?usp=email ) Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Gerrit-Change-Number: 84115 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 12:51:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2024