coreboot-gerrit August 2024

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/dcd2787e_88d7522e?us… : PS3, Line 406: pmc_clear_gpi_gpe0_status > I think pmc_clear_std_gpe1_status is gonna clear all GPE1 registers, so wondering if anything missin […] gpi_gpe0 means the general GPI event in GPE0. GPE1 only contains Intel's std events. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 22:39:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84104/comment/3247c0d3_d495dd79?us… : PS3, Line 10: ppe0 > gpe0 Done File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/33f08d7a_9730eab1?us… : PS3, Line 367: pmc_clear_std_gpe_status > I like this idea to use a single api to clear std gpe0 and gpe1. Done https://review.coreboot.org/c/coreboot/+/84104/comment/8770fb7f_a250e983?us… : PS3, Line 368: gpi > pmc_clear_std_gpe1_status? renamed to reset_std_gpe1_status() like the one for gpe0. https://review.coreboot.org/c/coreboot/+/84104/comment/cea5eb50_12399ab3?us… : PS3, Line 393: void pmc_clear_std_gpe1_status > Can this be instead pmc_clear_gpe1_status ? Unlike GPE0, you don't need the STD offset to be handled […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 22:35:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hannah Williams <hannah.williams(a)intel.com> Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Subrata Banik. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84104?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... soc/intel/common/block/pmc: Add GPE1 functions - Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag. - The existing static gpe functions has been renamed with gpe0. - Add gpe1 functions. BUG=362310295 TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT, and check if GPE1 sts bits have been printed during boot. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 66 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 6: (6 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/0693634b_1da9071a?us… : PS5, Line 29: GPE1_STS > > sure. will make the change. […] Subrata, One thing left is the case when GPE1 is support but we intend to use GPE0 with this Kconfig not selected, the defines here is duplicated. I add the #ifndef to support this case in the next patchset. Pls let me know what you think. thx. I also run into the same GPE1 defines issue on the next CL https://review.coreboot.org/c/coreboot/+/84104. I am doing the same for pmclib.c there. https://review.coreboot.org/c/coreboot/+/84103/comment/4d96ba44_9c12f2ba?us… : PS5, Line 31: > drop one space Acknowledged https://review.coreboot.org/c/coreboot/+/84103/comment/5748defd_bf77c4f7?us… : PS5, Line 31: > just use one space Acknowledged https://review.coreboot.org/c/coreboot/+/84103/comment/4d9b1486_ef5c494b?us… : PS5, Line 114: > one space Acknowledged https://review.coreboot.org/c/coreboot/+/84103/comment/52c53585_9ad63252?us… : PS5, Line 115: !fadt->gpe1_blk > we wish to program gpe1_blk_len if gpe1_blk is not zero. […] Acknowledged https://review.coreboot.org/c/coreboot/+/84103/comment/34729102_019e8a6b?us… : PS5, Line 116: GPE1_REG_MAX > not defined Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 21:44:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Bob Moragues (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Ren Kuo. Bob Moragues has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email ) Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... Patch Set 4: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 21:14:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PCIe root port driver
by Lean Sheng Tan (Code Review) 29 Aug '24

29 Aug '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81567?usp=email ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Add PCIe root port driver ...................................................................... soc/intel/xeon_sp: Add PCIe root port driver The driver sets ACPI names for PCIe root ports and its subordinate devices, and fill SSDT for them accordingly. SPR PCIe root port devices are initially supported. TEST=Build and boot on intel/archercity CRB Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/Makefile.mk A src/soc/intel/xeon_sp/pcie_root_port.c 2 files changed, 92 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 35b998c..4f87367 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -16,6 +16,7 @@ ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-y += numa.c ramstage-y += config.c +ramstage-y += pcie_root_port.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c diff --git a/src/soc/intel/xeon_sp/pcie_root_port.c b/src/soc/intel/xeon_sp/pcie_root_port.c new file mode 100644 index 0000000..fb9abde --- /dev/null +++ b/src/soc/intel/xeon_sp/pcie_root_port.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +static const char *pcie_device_get_acpi_name(const struct device *dev) +{ + /* + * dev->name cannot be assigned in this routine with const struct device *, + * instead, it is set up in pcie_device_set_acpi_name ahead of time. + */ + assert(dev->name); + return dev->name; +} + +static void soc_pciexp_scan_bridge(struct device *dev) +{ + if (CONFIG(PCIEXP_HOTPLUG)) { + unsigned int pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + u16 sltcap = pci_read_config16(dev, pciexpos + PCI_EXP_SLTCAP); + if (sltcap & PCI_EXP_SLTCAP_HPC) { + pciexp_hotplug_scan_bridge(dev); + return; + } + } else + pciexp_scan_bridge(dev); +} + +static void pcie_device_set_acpi_name(struct device *dev, const char *prefix) +{ + assert(prefix != NULL && strlen(prefix) == 2); + if (!prefix || strlen(prefix) != 2) + return; + + char *name = xmalloc(ACPI_NAME_BUFFER_SIZE); + uint8_t slot = PCI_SLOT(dev->path.pci.devfn); + uint8_t func = PCI_FUNC(dev->path.pci.devfn); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%02X", prefix, PCI_DEVFN(slot, func)); + dev->name = name; +} + +static void pcie_root_port_init(struct device *rp) +{ + if (!is_pci_bridge(rp)) + return; + + pcie_device_set_acpi_name(rp, "RP"); + + struct device *dev = NULL; + while ((dev = dev_bus_each_child(rp->downstream, dev))) { + if (!is_pci(dev)) + continue; + pcie_device_set_acpi_name(dev, "DC"); + } + + pci_dev_init(rp); +} + +static const unsigned short pcie_root_port_ids[] = { + /* + * Refer to https://pcisig.com/developers/integrators-list?field_il_comp_product_type_v… + */ + 0x352a, + 0x352b, + 0x352c, + 0x352d, + 0x347a, + 0 +}; + +static struct device_operations pcie_root_port_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = soc_pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .init = pcie_root_port_init, + .ops_pci = &soc_pci_ops, + .acpi_fill_ssdt = &acpigen_write_pci_root_port, + .acpi_name = &pcie_device_get_acpi_name, +}; + +static const struct pci_driver pcie_root_port_driver __pci_driver = { + .ops = &pcie_root_port_ops, + .vendor = PCI_VID_INTEL, + .devices = pcie_root_port_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 14 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Subrata Banik (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Ren Kuo. Subrata Banik has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email ) Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brox/variants/jubilant/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84124/comment/f5e7ec3d_dc66be98?us… : PS4, Line 25: register "pmc_gpe0_dw1" = "GPP_F" > > if wake sources are scattered across more than 3 GPIO bank then you can use GPIO Tier 1 register to add additional entries. > > I am not seeing any precedence for that. Also chip config does not seem to support more than 3 entries. It seems we need to configure PMC as well as GPIO communities for every tier. Should I ask Intel's support on this one? Here is my understanding (I misspoke in my previous reply, the GPIOs in question are referred to as Tier 2 GPIOs). There are two ways to configure GPIO events. 1. Using Tier 1, we can configure up to 3 GPIO banks. 2. We can configure those banks as SCI, which allows them to generate GPE. There are GPE registers 0-127, of which 0-95 are configurable and 96-127 are generic. 3. If we need more GPIOs to be configured as GPE, we need to move them to GPIO Tier 2 programming. I don't see the register details for this in the EDS, but I believe you can ask Intel for information on how to configure additional PADs as Tier 2 GPIOs to register GPE. 4. The Tier 2 GPEs are considered a MUX'ed GPE, where General Purpose Event 0 Status [127:96] register bit 15 is used for GPIO_TIER2_SCI_STATUS (and GPIO_TIER2_SCI_EN likewise). ``` GPIO Tier2 SCI EN (GPIO_TIER2_SCI_EN) Used to enable the setting of GPIO_TIER2_SCI_STS to generate wake/SCI#. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 18:43:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in libgfxinit[main]: gma display_probing: Make new TGL ports available
by Nico Huber (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Elyes Haouas, Paul Menzel, Thomas Heijligen. Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/libgfxinit/+/81522?usp=email ) Change subject: gma display_probing: Make new TGL ports available ...................................................................... Patch Set 7: (1 comment) File common/hw-gfx-gma-display_probing.adb: https://review.coreboot.org/c/libgfxinit/+/81522/comment/afe19fa6_ddd8c6b5?… : PS7, Line 38: function Sibling_Port (Port : Port_Type) return Port_Type is > Hmmmmm, wait. […] Yep, the new naming makes this more obvious. The TC ports can also be implemented as DP and HDMI at the same time. So in theory, can suffer from the same issues. (though, I have to admit that I only saw this with 10y old ThinkPad docks where you really can physically connect two competing displays at the same time) -- To view, visit https://review.coreboot.org/c/libgfxinit/+/81522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I9d96673f931be0086536044694ecd127ba2a823d Gerrit-Change-Number: 81522 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 29 Aug 2024 18:31:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Karthik Ramasubramanian (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Nick Vaccaro, Ren Kuo, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email ) Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brox/variants/jubilant/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84124/comment/6f4b4b87_8e5d2b68?us… : PS4, Line 25: register "pmc_gpe0_dw1" = "GPP_F" > if wake sources are scattered across more than 3 GPIO bank then you can use GPIO Tier 1 register to add additional entries. I am not seeing any precedence for that. Also chip config does not seem to support more than 3 entries. It seems we need to configure PMC as well as GPIO communities for every tier. Should I ask Intel's support on this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 18:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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