coreboot-gerrit August 2024

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[L] Change in coreboot[main]: vc/intel/fsp2_0: Add Skeleton FSP header for PTL
by Saurabh Mishra (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Saurabh Mishra, Subrata Banik. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83732?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: vc/intel/fsp2_0: Add Skeleton FSP header for PTL ...................................................................... vc/intel/fsp2_0: Add Skeleton FSP header for PTL Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h 6 files changed, 500 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83732/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Gerrit-Change-Number: 83732 Gerrit-PatchSet: 4 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/hatch: Add FP enable for Dratini
by Jon Murphy (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nick Vaccaro, Subrata Banik. Hello Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83745?usp=email to look at the new patch set (#3). Change subject: mb/google/hatch: Add FP enable for Dratini ...................................................................... mb/google/hatch: Add FP enable for Dratini Add FP enable/disable based on SKU ID for Dratini. This is meant to resolve a UMA issue with Dratini devices that had the FPMCU populated on non-fp devices. Since the FPMCU is present, and the firmware enables the power GPIO's based on variant, not SKU, the devices were reporting data on fingerprint errantly. BUG=b:354769653 TEST=Flash to Dratini, test FP. Disable test SKU, flash on Dratini, test FP. Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/hatch/variants/dratini/include/variant/sku.h M src/mainboard/google/hatch/variants/dratini/ramstage.c 2 files changed, 29 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/83745/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0 Gerrit-Change-Number: 83745 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar. Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email ) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82682/comment/fdf719b2_291de276?us… : PS8, Line 7: mb/google/nissa > soc/intel/adl? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 04:11:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Hello Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82682?usp=email to look at the new patch set (#10). Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting According to RDC#646929 Power Map, there are two expected values of VccInAuxImonIccImax and the value has to align with HW design. But in current code, vccin_aux_imon_iccmax hard code to 27000(27A), hence, provide a config for projects modification. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and confirm the value changed Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intelalderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Hello Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82682?usp=email to look at the new patch set (#9). Change subject: soc/intelalderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... soc/intelalderlake: Add Vccin Aux Imon Iccmax setting According to RDC#646929 Power Map, there are two expected values of VccInAuxImonIccImax and the value has to align with HW design. But in current code, vccin_aux_imon_iccmax hard code to 27000(27A), hence, provide a config for projects modification. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and confirm the value changed Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 9 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config
by David Wu (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/83720?usp=email ) Change subject: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/riven/fw_config.c: https://review.coreboot.org/c/coreboot/+/83720/comment/1442b875_bbba9f3f?us… : PS1, Line 70: if (!fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_CNVI))) { > should we check […] It will cause boot fail with "ASSERTION ERROR:file `src/soc/intel/alderlake/fsp_params.c`, line 820", seem like CB:83148. When fw_config is unprovisioned (CNVi WIFI is disabled), CNVi BT must be turned off. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/83720?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb925c02c73d3630be8b78debf608270b08854fe Gerrit-Change-Number: 83720 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Aug 2024 04:07:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/hatch: Add FP enable for Dratini
by Jon Murphy (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nick Vaccaro, Subrata Banik. Hello Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83745?usp=email to look at the new patch set (#2). Change subject: mb/google/hatch: Add FP enable for Dratini ...................................................................... mb/google/hatch: Add FP enable for Dratini Add FP enable/disable based on SKU ID for Dratini. This is meant to resolve a UMA issue with Dratini devices that had the FPMCU populated on non-fp devices. Since the FPMCU is present, and the firmware enables the power GPIO's based on variant, not SKU, the devices were reporting data on fingerprint errantly. BUG=b:354769653 BUG=b:200825114 TEST=Flash to Dratini, test FP. Disable test SKU, flash on Dratini, test FP. Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/hatch/variants/dratini/include/variant/sku.h M src/mainboard/google/hatch/variants/dratini/ramstage.c 2 files changed, 25 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/83745/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0 Gerrit-Change-Number: 83745 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[NoOp] Change in coreboot[main]: TEST: add 0arr.c
by Xixi Chen (Code Review) 02 Aug '24

02 Aug '24

Xixi Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83747?usp=email ) Change subject: TEST: add 0arr.c ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/83747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa7acf7eb889418abd55e3224c9670f263a9d372 Gerrit-Change-Number: 83747 Gerrit-PatchSet: 1 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in blobs[main]: soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1
by Xixi Chen (Code Review) 02 Aug '24

02 Aug '24

Xixi Chen has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/83748?usp=email ) Change subject: soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1 ...................................................................... soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1 For fast-k RX flow, Vref value is readed from the MRC_CACHE, but the preferred RX Vref value 0xE is set, with no re-calibration. It may cause RX window margin smaller. Re-read the RX Vref value from MRC_CACHE to fix the issue. BUG=b:352632973 TEST=Check the fast-k RX Vref value is normal Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: Id7df502346d590d3cf3827f48d868da021f6ec9d --- M soc/mediatek/mt8186/dram.elf M soc/mediatek/mt8186/dram.elf.md5 M soc/mediatek/mt8186/dram_release_notes.txt 3 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/48/83748/1 diff --git a/soc/mediatek/mt8186/dram.elf b/soc/mediatek/mt8186/dram.elf index 0f80e3d..9c5b497 100644 --- a/soc/mediatek/mt8186/dram.elf +++ b/soc/mediatek/mt8186/dram.elf Binary files differ diff --git a/soc/mediatek/mt8186/dram.elf.md5 b/soc/mediatek/mt8186/dram.elf.md5 index 97bbb16..f14db25 100644 --- a/soc/mediatek/mt8186/dram.elf.md5 +++ b/soc/mediatek/mt8186/dram.elf.md5 @@ -1 +1 @@ -5c7f96716ec681544803301184a33f4b *dram.elf +ea3a4ae5539d3ba895f09285d9e42317 *dram.elf diff --git a/soc/mediatek/mt8186/dram_release_notes.txt b/soc/mediatek/mt8186/dram_release_notes.txt index 16e773d..e75a169 100644 --- a/soc/mediatek/mt8186/dram_release_notes.txt +++ b/soc/mediatek/mt8186/dram_release_notes.txt @@ -1,3 +1,11 @@ +# 0.1.1 + +Included changes: + +Codebase updates to: CL*6306734: mt8188: Bump FIRMWARE_BUILD_VER to 2 + +- CL:*7546745: mtk-dramk/mt8186: Fix fast-k RX Vref smaller issue + # 0.1.0 1. A local build. -- To view, visit https://review.coreboot.org/c/blobs/+/83748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Id7df502346d590d3cf3827f48d868da021f6ec9d Gerrit-Change-Number: 83748 Gerrit-PatchSet: 1 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com>

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[NoOp] Change in coreboot[main]: TEST: add 0arr.c
by Xixi Chen (Code Review) 02 Aug '24

02 Aug '24

Xixi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83747?usp=email ) Change subject: TEST: add 0arr.c ...................................................................... TEST: add 0arr.c Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: Ifa7acf7eb889418abd55e3224c9670f263a9d372 --- A 0arr.c 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83747/1 diff --git a/0arr.c b/0arr.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/0arr.c -- To view, visit https://review.coreboot.org/c/coreboot/+/83747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa7acf7eb889418abd55e3224c9670f263a9d372 Gerrit-Change-Number: 83747 Gerrit-PatchSet: 1 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com>

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coreboot-gerrit August 2024