coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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3913 discussions

[M] Change in coreboot[main]: util/autoport: Put devicetree devices above chips
by Angel Pons (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nicholas Chin, Nico Huber. Angel Pons has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/82406?usp=email ) Change subject: util/autoport: Put devicetree devices above chips ...................................................................... Patch Set 5: (1 comment) File util/autoport/main.go: https://review.coreboot.org/c/coreboot/+/82406/comment/22d2c96c_fe2727d1?us… : PS3, Line 307: MatchDev(&dev.Children[idx]) > Probably not. I just shuffled things around until the devicetree looked the way I wanted. Updated but haven't had the chance to test. -- To view, visit https://review.coreboot.org/c/coreboot/+/82406?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dc2ff13182ff9d92141b1736796749cea49d23a Gerrit-Change-Number: 82406 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 08:06:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: util/autoport: Use sudo to call log-making programs
by Angel Pons (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nicholas Chin, Nico Huber. Angel Pons has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/82404?usp=email ) Change subject: util/autoport: Use sudo to call log-making programs ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf4ddf8dd2cb930e9b7303e2ea986d8c072aa7a Gerrit-Change-Number: 82404 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 08:04:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/autoport: Streamline external program invocation
by Angel Pons (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nicholas Chin, Nico Huber, Patrick Rudolph. Angel Pons has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/82403?usp=email ) Change subject: util/autoport: Streamline external program invocation ...................................................................... Patch Set 5: (4 comments) File util/autoport/log_maker.go: https://review.coreboot.org/c/coreboot/+/82403/comment/01601eff_51c35405?us… : PS1, Line 46: WriteString > Oh, right, I already have a println in the right place Done https://review.coreboot.org/c/coreboot/+/82403/comment/01144ec4_0f675637?us… : PS1, Line 66: Fatal > I know, it's intentional. Original code did the same but not in all cases (which is odd). […] Ack File util/autoport/log_maker.go: https://review.coreboot.org/c/coreboot/+/82403/comment/a7f5bf9f_d5535bf5?us… : PS3, Line 162: The following tool > This would be way out of order now. Easy way would be to adapt the text, explain […] Updated the text for now, as I don't know the golang syntax. I can adapt this in a follow-up if need be. https://review.coreboot.org/c/coreboot/+/82403/comment/9be6e879_0a94acb2?us… : PS3, Line 190: "" > This is intentional, as the programs are more likely to be in PATH than in CWD. […] Done. Also explained why we look for coreboot utils in the utils folder first. -- To view, visit https://review.coreboot.org/c/coreboot/+/82403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I144bdf609e0aebd8f6ddebc0eb1216bedebfa313 Gerrit-Change-Number: 82403 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 08:02:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: util/autoport: Streamline external program invocation
by Angel Pons (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Angel Pons, Nicholas Chin, Nico Huber, Patrick Rudolph. Hello Nicholas Chin, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82403?usp=email to look at the new patch set (#5). Change subject: util/autoport: Streamline external program invocation ...................................................................... util/autoport: Streamline external program invocation The original approach to call external programs was rather convoluted and would fall back to running executables inside the current working directory if running them from the location specified in the code did not succeed, swallowing any errors from the first invocation. Rewrite the system around the `LogMakingProgram` concept, a struct to represent a program. Each program has a name, prefixes to try running it from and the arguments to pass to it (if any). Plus, collect error information from failed executions, but only show it when none of the prefixes resulted in a successful invocation. In addition, look for programs in PATH instead of CWD: it is unlikely that all utils will be in the CWD, but utils can be in the PATH after one installs them (`sudo make install`). For coreboot utils, look for them in the utils folder first as the installed versions might not be up-to-date. Furthermore, print out the command about to be executed, as there are some commands (e.g. `ectool` on boards without an EC) that can take a very long time to complete. Change-Id: I144bdf609e0aebd8f6ddebc0eb1216bedebfa313 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/log_maker.go 1 file changed, 72 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/82403/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I144bdf609e0aebd8f6ddebc0eb1216bedebfa313 Gerrit-Change-Number: 82403 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PCIe root port driver
by Shuo Liu (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81567?usp=email to look at the new patch set (#11). Change subject: soc/intel/xeon_sp: Add PCIe root port driver ...................................................................... soc/intel/xeon_sp: Add PCIe root port driver The driver sets ACPI names for PCIe root ports and its subordinate devices, and fill SSDT for them accordingly. SPR PCIe root port devices are initially supported. TEST=Build and boot on intel/archercity CRB Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/pcie_root_port.c 3 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81567/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PCIe root port driver
by Shuo Liu (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/81567?usp=email ) Change subject: soc/intel/xeon_sp: Add PCIe root port driver ...................................................................... Patch Set 10: (2 comments) File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/81567/comment/b0865e6e_f27e2bfe?us… : PS9, Line 116: pcie_device_set_acpi_name > Is this going to be called from other parts as well? […] Done File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/81567/comment/c0ef4b09_46843378?us… : PS9, Line 474: > would be nice to have this in a separate file Good suggestion, updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 07:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PCIe root port driver
by Shuo Liu (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81567?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add PCIe root port driver ...................................................................... soc/intel/xeon_sp: Add PCIe root port driver The driver sets ACPI names for PCIe root ports and its subordinate devices, and fill SSDT for them accordingly. SPR PCIe root port devices are initially supported. TEST=Build and boot on intel/archercity CRB Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/pcie_root_port.c 3 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81567/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nicholas Chin. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: Intel Alder Lake-N N100 processor 8GB LPDDR5 memory 64GB eMMC storage SO-DIMM 260-pin connector for function expansion This commit includes: Basic board configuration Memory initialization Essential I/O setup TODO: Verify and fine-tune ACPI tables Test and optimize power management Implement advanced features specific to this board Testing with Lite carrier board Booting into default installed Windows: Passed Installing Ubuntu 22.04: Failed (system shuts down, unable to auto-reboot) USB 3.0/2.0: Working HDMI output: Working S3 sleep mode: Failed Power on after shutdown: Failed (requires power removal) Ethernet port: Not working UART of SuperIO in OS: Missing Environment Controller: Not supported Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/empty.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 22 files changed, 874 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 3 Gerrit-Owner: KunYi Chen Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO high range
by Shuo Liu (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83538?usp=email to look at the new patch set (#4). Change subject: soc/intel/xeon_sp: Reserve MMIO high range ...................................................................... soc/intel/xeon_sp: Reserve MMIO high range Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will assign domain MMIO high windows from this range. However, there will be unassigned parts among these high windows for non-domain device usage (e.g. misc devices belonged to an IIO stack but not belonged to any PCIe domains under that stack). This will cause segmentation in MTRR UC coverage. Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR calculation, this reservation will connect the discontinued domain MMIO high windows together to form one continuous range, and save MTRR register usage from inadequacy. This change is initially raised for SPR but could be effective for GNR as well. TESTED = Build and boot in intel/archercity CRB, MTRR register usage decreases from 7 to 3 in 2S system. TESTED = Only setting MTRR for below 4GB ranges test fails with LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb) tsc: Detected 2000.000 MHz processor last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 ... Call Trace: ? 0xffffffff8f600000 ? setup_arch+0x4bb/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 ---[ end trace 0e56686fd458f0c5 ]--- update e820 for mtrr modified physical RAM map: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved ... modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved last_pfn = 0x6354e max_arch_pfn = 0x10000000000 Memory KASLR using RDRAND RDTSC... x2apic: enabled by BIOS, switching to x2apic ops Using GB pages for direct mapping ... Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] DMA zone: 28769 pages in unavailable ranges DMA32 zone: 19122 pages in unavailable ranges BUG: unable to handle page fault for address: ff24b56eba60cff8 BAD Oops: 0000 [#1] SMP NOPTI CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 ... Call Trace: ? set_pte_vaddr_p4d+0x24/0x35 ? __native_set_fixmap+0x21/0x28 ? map_vsyscall+0x35/0x56 ? setup_arch+0xa00/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb CR2: ff24b56eba60cff8 ---[ end trace 0e56686fd458f0c6 ]--- RIP: 0010:fill_pud+0xa/0x62 ... Kernel panic - not syncing: Attempted to kill the idle task! ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 6 files changed, 51 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83538/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Gerrit-Change-Number: 83538 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO high range
by Shuo Liu (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email ) Change subject: soc/intel/xeon_sp: Reserve MMIO high range ...................................................................... Patch Set 2: (4 comments) Patchset: PS2: > Side note: This whole situation is becoming too messy for my taste. Especially […] The cause is around FSP's two layer IIO resource allocation structure (IIO stack -> PCIe domains). I need to bring the inputs internally for some discussion, while this CL could help in SPR and GNR timeframe to save further efforts here. Another aspect is that, if other SoCs has similar needs of using MMIO high, maybe some common changes could be justified then? Commit Message: https://review.coreboot.org/c/coreboot/+/83538/comment/18c53a6c_2ad7ddf1?us… : PS1, Line 7: soc/intel/xeon_sp: Reserve FSP MMIO high window > > GNR and later SoC also fit. […] Sorry for being busy with some affairs recent days and I'm glad that some dedicated time today could be reserved for discussion :-) For 'non PCI domain MMIOs', they are used for misc devices belonged to an IIO stack but not belonged to any PCIe domains under that stack. For Gen6, VTd BAR is counted to this class, similarly is the CXL host bridge control register BAR. Not like Gen1 (https://review.coreboot.org/c/coreboot/+/83136), in Gen6, all these misc BARs do not needs to be explicitly reserved anymore. This CL (https://review.coreboot.org/c/coreboot/+/83538) is initially raised for SPR, but also will help GNR. I updated the commit message and not sure if that could be clearer. https://review.coreboot.org/c/coreboot/+/83538/comment/80757e69_48f78c7c?us… : PS1, Line 19: is especially important : on systems with 2 or more sockets, where each socket has multiple : domains. > Well, you could also tell it to use WB default instead. But I get it, Linux […] Sure, updated the commit message. File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/83538/comment/4c177fbc_9cc62e2b?us… : PS2, Line 371: * MMIO high window has to be added in set_resources instead of read_resources : * due to that adding in read_resources will cause the whole window reserved : * and cannot be used for resource allocation. > ```suggestion […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Gerrit-Change-Number: 83538 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 07:34:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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