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Change subject: mb/emulation/qemu-riscv: Add support for 512 harts
......................................................................
mb/emulation/qemu-riscv: Add support for 512 harts
QEMU has a maximum of 512 of emulated harts supported.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1
---
M src/lib/Makefile.mk
M src/mainboard/emulation/qemu-riscv/Kconfig
M src/mainboard/emulation/qemu-riscv/Makefile.mk
M src/mainboard/emulation/qemu-riscv/memlayout.ld
A src/mainboard/emulation/qemu-riscv/smp.c
5 files changed, 37 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81083/6
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Add weak function for SMP hart count
......................................................................
Add weak function for SMP hart count
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587
---
M src/arch/riscv/Kconfig
M src/arch/riscv/include/arch/smp/smp.h
M src/arch/riscv/smp.c
3 files changed, 57 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81082/4
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Change subject: commonlib/device_tree.c: Remove incorrect warning
......................................................................
commonlib/device_tree.c: Remove incorrect warning
Currently a warning is printed even if the maximum amount of nodes is
not exceeded.
Remove the warning, since in most cases the maximum amount of nodes
for a given prefix is usually well known. For example the /cpu nodes
always have a maximum of CONFIG_MAX_CPUS.
One may also just want to read the first X amount of nodes matching a
given prefix.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ic1111e8acb72ea1e9159da0d8386f40cbbdbc63f
---
M src/commonlib/device_tree.c
1 file changed, 2 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/83085/5
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Change subject: mb/hp: Add Compaq Elite 8300 CMT port
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79745/comment/a2ec780e_b7256c8c?us… :
PS15, Line 65: device ref pcie_rp5 on end
Here's your "duplicate device". We used to allow this to model devices with
multiple downstream buses. Now the mistake is more obvious, error message
could be better of course.
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Change subject: [UNTESTED] Makefile: Move `--no-warn-rwx-segments' into xcompile
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> No problem if you think that 'util/xcompile/xcompile' is the right place for GCC FLAGs
It's the right place for any flag that we need to set and that is not supported
by all toolchain versions.
If we'd leave it to that (Felix probably won't), I don't think it would get too
bloated. Still I reasoned a bit about a timeframe: Things seemed to work with-
out much noise when we updated the compiler every 2~3 years. Assuming there's
always somebody who doesn't update every time, I'd say we can move things after
6 years. That should also fit the timeframe of Debian support running out for
old toolchains.
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Attention is currently required from: Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelley Chen, Subrata Banik.
Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelley Chen, Subrata Banik,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brox: Boot to kernel without battery
......................................................................
mb/google/brox: Boot to kernel without battery
Set Boot frequency UPD to 1 to avoid higher PL2 power draw when
only adaptor is connected with battery removed or disconnected.
Reduce PL4 value to overcome power spikes from SoC during boot.
Remove Psys implementation since it impacts active state platform
performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W,45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 59 insertions(+), 104 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/3
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Change subject: src/lib/malloc.c: If allocation fails, leave the heap unchanged
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
File src/lib/malloc.c:
https://review.coreboot.org/c/coreboot/+/83475/comment/0dc23f42_adc90521?us… :
PS1, Line 29: unsigned long
`(uintptr_t)`, which is technically the same for our targets, would make the intention clearer.
https://review.coreboot.org/c/coreboot/+/83475/comment/7cfc7264_729a73dc?us… :
PS1, Line 34: printk(BIOS_ERR, "Tried to round up free_mem_ptr %p to %p\n",
: free_mem_ptr, p);
I think the message text just didn't make sense, the printed numbers did though.
Because it was the new `free_mem_ptr` (now `p + size`) that conflicted with
`free_mem_end_ptr`. With the current PS you could get prints like
```
Tried to round up free_mem_ptr 0x1234 to 0x1300 but free_mem_end_ptr is 0x2000
```
```suggestion
printk(BIOS_ERR, "Tried to increase free_mem_ptr %p to %p\n",
free_mem_ptr, p + size);
```
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