coreboot-gerrit August 2024

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[XS] Change in coreboot[main]: security/vboot: Include new gbb flag to enforce CSE sync
by Felix Held (Code Review) 02 Aug '24

02 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83685?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: security/vboot: Include new gbb flag to enforce CSE sync ...................................................................... security/vboot: Include new gbb flag to enforce CSE sync This patch adds a GBB flag to coreboot, which, when enabled, enforces CSE sync even if the current CSE version matches the version in CBFS. The CSME sync GBB and flag are designed to enhance autotest functionalities and are not intended or recommended for use in developing any other features. BUG=b:353053317 TEST=futility gbb --help Cq-Depend: chromium:5718196 Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83685 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.mk 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e30e8ee..7e291e0 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -451,6 +451,10 @@ bool "Enable USB Device Controller" default n +config GBB_FLAG_FORCE_CSE_SYNC + bool "Running tests; enforce CSE sync" + default n + endmenu # GBB menu "Vboot Keys" diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk index 48a6c9d..e9b3eb6 100644 --- a/src/security/vboot/Makefile.mk +++ b/src/security/vboot/Makefile.mk @@ -265,6 +265,7 @@ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY),0x4000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_ENABLE_UDC),0x10000) \ + $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_CSE_SYNC),0x20000) \ ) ifneq ($(CONFIG_GBB_BMPFV_FILE),) -- To view, visit https://review.coreboot.org/c/coreboot/+/83685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9 Gerrit-Change-Number: 83685 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Felix Held (Code Review) 02 Aug '24

02 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83733?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id 4b12d392e5b1: scripts: Add a script to convert a vbprivk to a PEM to commit id f1f70f46dc54: 2lib: Add gbb flag to enforce CSE sync -Subproject commit 4b12d392e5b12de29c582df4e717b1228e9f1594 +Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2 Change-Id: I2c5b603ce5ea49e6c1aec293960184d84eedd1e7 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83733 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index 4b12d39..f1f70f4 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 4b12d392e5b12de29c582df4e717b1228e9f1594 +Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5b603ce5ea49e6c1aec293960184d84eedd1e7 Gerrit-Change-Number: 83733 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: i2c/drivers/generic: Return ROTM in a package
by Felix Held (Code Review) 02 Aug '24

02 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83721?usp=email ) Change subject: i2c/drivers/generic: Return ROTM in a package ...................................................................... i2c/drivers/generic: Return ROTM in a package The ROTM method should return a package: ``` Name (RBUF, Package (0x03) { "0 1 0", "1 0 0", "0 0 1" }) Return (RBUF) ``` Adjust the acpigen to do this. Change-Id: Id493f6955c1d0dc3449402262a8575091a828226 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/i2c/generic/generic.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 1875bac..27bef49 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -149,6 +149,7 @@ /* Rotation Matrix */ if (config->has_rotation_matrix) { acpigen_write_method("ROTM", 0); + acpigen_write_name("RBUF"); acpigen_write_package(3); for (int i = 0; i < 3; i++) { @@ -160,6 +161,8 @@ acpigen_write_string(matrix_row); } + acpigen_pop_len(); + acpigen_write_return_namestr("RBUF"); acpigen_pop_len(); acpigen_pop_len(); -- To view, visit https://review.coreboot.org/c/coreboot/+/83721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id493f6955c1d0dc3449402262a8575091a828226 Gerrit-Change-Number: 83721 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/ti/am335x: Change and optimize memlayout
by Felix Held (Code Review) 02 Aug '24

02 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70160?usp=email ) Change subject: soc/ti/am335x: Change and optimize memlayout ...................................................................... soc/ti/am335x: Change and optimize memlayout Clang builds (bootblock: 20800 bytes) are slightly larger than GCC builds (bootblock: 18688 bytes) so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. To be able to link the clang bootblock increase it from 20K to 22K. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/ti/beaglebone/board.fmd M src/soc/ti/am335x/memlayout.ld 2 files changed, 9 insertions(+), 9 deletions(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/ti/beaglebone/board.fmd b/src/mainboard/ti/beaglebone/board.fmd index 0656b85..26a210f 100644 --- a/src/mainboard/ti/beaglebone/board.fmd +++ b/src/mainboard/ti/beaglebone/board.fmd @@ -1,6 +1,6 @@ FLASH@0x000 32M { BIOS@0x0 109K { - BOOTBLOCK@0x0 20K + BOOTBLOCK@0x0 22K } PAYLOAD { diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 8d1e8d6..b9d01a8 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -7,15 +7,15 @@ SECTIONS { SRAM_START(0x402f0400) - BOOTBLOCK(0x402f0400, 20K) - FMAP_CACHE(0x402f0400+20K, 2K) - CBFS_MCACHE(0x402f0400+20K+2K, 8K) - TTB(0x402F8000, 16K) - ROMSTAGE(0x402F8000+16K, 40K) + BOOTBLOCK(., 22K) + FMAP_CACHE(., 2K) + CBFS_MCACHE(., 8K) + ROMSTAGE(., 42K) + PRERAM_CBFS_CACHE(., 20K) - PRERAM_CBFS_CACHE(0x402F8000+16K+40K, 20K) - - STACK(0x4030be00, 4K) + STACK(., 4K) + . = ALIGN(16K); + TTB(., 16K) SRAM_END(0x40310000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/70160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Gerrit-Change-Number: 70160 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: arch/riscv: Refactor SMP code
by Maximilian Brune (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Philipp Hug, Ron Minnich. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81082?usp=email ) Change subject: arch/riscv: Refactor SMP code ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81082/comment/c9569327_4c0dc3a1?us… : PS1, Line 8: > needs updating Done File src/arch/riscv/smp.c: https://review.coreboot.org/c/coreboot/+/81082/comment/3ab3034d_b88bbc3f?us… : PS2, Line 56: //TODO not sure if we need a timeout here or if the time waiting for smp_resume to be called is enough of a timeout > take care of that. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587 Gerrit-Change-Number: 81082 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 14:08:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: arch/riscv/include/mcall.h: Remove unused
by Maximilian Brune (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Philipp Hug, Ron Minnich. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83754?usp=email ) Change subject: arch/riscv/include/mcall.h: Remove unused ...................................................................... arch/riscv/include/mcall.h: Remove unused Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ic633899dd476e1062bb805222bc6b02af4d47bd6 --- M src/arch/riscv/include/mcall.h M src/arch/riscv/smp.c 2 files changed, 7 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83754/1 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 69eb574..eec8a8c 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -3,14 +3,12 @@ #ifndef _MCALL_H #define _MCALL_H -// NOTE: this is the size of struct hls below. A static_assert would be -// nice to have. #if __riscv_xlen == 64 -#define HLS_SIZE 96 +#define HLS_SIZE 64 #endif #if __riscv_xlen == 32 -#define HLS_SIZE 56 +#define HLS_SIZE 48 #endif /* We save 37 registers, currently. */ @@ -22,26 +20,13 @@ #include <arch/smp/atomic.h> #include <stdint.h> -struct sbi_device_message { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; -}; - struct blocker { void *arg; void (*fn)(void *arg); - atomic_t sync_a; - atomic_t sync_b; + atomic_t sync; }; struct hls { - struct sbi_device_message *device_request_queue_head; - unsigned long device_request_queue_size; - struct sbi_device_message *device_response_queue_head; - struct sbi_device_message *device_response_queue_tail; - int enabled; int hart_id; int ipi_pending; diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 811719e..eb3c6cc 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -17,14 +17,14 @@ set_msip(hartid, 0); // clear pending interrupts write_csr(mie, MIP_MSIP); // enable only IPI (for smp_resume) barrier(); - atomic_set(&HLS()->entry.sync_a, 0x01234567); // mark the hart as sleeping. + atomic_set(&HLS()->entry.sync, 0x01234567); // mark the hart as sleeping. // pause hart do { __asm__ volatile ("wfi"); // wait for interrupt } while ((read_csr(mip) & MIP_MSIP) == 0); - atomic_set(&HLS()->entry.sync_a, 0); // mark the hart as awake + atomic_set(&HLS()->entry.sync, 0); // mark the hart as awake HLS()->entry.fn(HLS()->entry.arg); } } @@ -51,7 +51,7 @@ if (i == working_hartid) continue; - if (atomic_read(&OTHER_HLS(i)->entry.sync_a) != 0x01234567) { + if (atomic_read(&OTHER_HLS(i)->entry.sync) != 0x01234567) { /* * we assmue here that the time between smp_pause and smp_resume * is enough for all harts to reach the smp_pause state. @@ -77,7 +77,7 @@ continue; // wait for hart to publish its waking state - while (atomic_read(&OTHER_HLS(i)->entry.sync_a) != 0) + while (atomic_read(&OTHER_HLS(i)->entry.sync) != 0) ; count_awake_harts++; } -- To view, visit https://review.coreboot.org/c/coreboot/+/83754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic633899dd476e1062bb805222bc6b02af4d47bd6 Gerrit-Change-Number: 83754 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: mb/emulation/qemu-riscv: Add support for 512 harts
by Maximilian Brune (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Maximilian Brune, Philipp Hug, Ron Minnich. Hello Philipp Hug, Ron Minnich, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81083?usp=email to look at the new patch set (#7). Change subject: mb/emulation/qemu-riscv: Add support for 512 harts ...................................................................... mb/emulation/qemu-riscv: Add support for 512 harts QEMU has a maximum of 512 of emulated harts supported. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1 --- M src/commonlib/Makefile.mk M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/memlayout.ld A src/mainboard/emulation/qemu-riscv/smp.c 5 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81083/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1 Gerrit-Change-Number: 81083 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[M] Change in coreboot[main]: arch/riscv: Refactor SMP code
by Maximilian Brune (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Philipp Hug, Ron Minnich. Hello Philipp Hug, Ron Minnich, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81082?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: Refactor SMP code ...................................................................... arch/riscv: Refactor SMP code Currently only a fixed number of harts/cores can be detected. This patch adds a Kconfig option which allows to detect the number of harts at runtime if a SOC or mainboard has a scheme to do so. As part of that patch SMP logic has been mostly moved to smp_resume, since it is easier to debug issues at the time smp_resume is called than it is at smp_pause, since the serial is usually not present at the time of the first smp_pause call. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587 --- M src/arch/riscv/Kconfig M src/arch/riscv/include/arch/smp/smp.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c M src/arch/riscv/smp.c 5 files changed, 84 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81082/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587 Gerrit-Change-Number: 81082 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: soc/inte/cnvi: Add AOLX Method
by Matt DeVillier (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83716?usp=email ) Change subject: soc/inte/cnvi: Add AOLX Method ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/cnvi/cnvi.c: https://review.coreboot.org/c/coreboot/+/83716/comment/aac77c6b_7b70aa78?us… : PS5, Line 330: // TODO: If AO enabled, write 1 write 1 to where? -- To view, visit https://review.coreboot.org/c/coreboot/+/83716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeafb2b6e8a702430dcf10eb28bfeb9f77aa29b4 Gerrit-Change-Number: 83716 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 02 Aug 2024 13:58:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cnvi: Add GBTE Method
by Matt DeVillier (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83715?usp=email ) Change subject: soc/intel/cnvi: Add GBTE Method ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/soc/intel/common/block/cnvi/cnvi.c: https://review.coreboot.org/c/coreboot/+/83715/comment/f2416ab0_6886e6bd?us… : PS5, Line 300: 0x090a0000 do we have any idea where this value comes from? -- To view, visit https://review.coreboot.org/c/coreboot/+/83715?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f6b97b0961579f36cd053b0252213c3335b1c62 Gerrit-Change-Number: 83715 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 02 Aug 2024 13:58:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit August 2024