Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83746?usp=email )
Change subject: mb/google/brya/var/trulo: Remove mux references from typec port
......................................................................
mb/google/brya/var/trulo: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 1 insertion(+), 12 deletions(-)
Approvals:
Dinesh Gehlot: Looks good to me, approved
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index d7fca12..510053f 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -525,21 +525,10 @@
device ref uart0 on end
device ref pch_espi on
chip ec/google/chromeec
- use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
- device ref pmc hidden
- chip drivers/intel/pmc_mux
- device generic 0 on
- chip drivers/intel/pmc_mux/conn
- use usb2_port5 as usb2_port
- use tcss_usb3_port1 as usb3_port
- device generic 0 alias conn0 on end
- end
- end
- end
- end
+ device ref pmc hidden end
device ref hda on
chip drivers/sof
register "spkr_tplg" = "max98360a"
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Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82682/comment/bbc302e8_b64c29ce?us… :
PS10, Line 17: confirm
> Add a printk to output a debug message after the line below to observe whether the value is changing […]
Done
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Hello Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................
soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.
But in current code, vccin_aux_imon_iccmax hard code to 27000(27A),
hence, provide a config for projects modification.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and add a printk to output a debug message
to observe whether the value is changing as expected.
Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 10 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/11
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Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82682/comment/9db0364a_6dd669ca?us… :
PS10, Line 17: confirm
> It would be good if you share the method with test results on how value change verified.
Add a printk to output a debug message after the line below to observe whether the value is changing as expected.
```
s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax(config) * 4 / MILLIAMPS_TO_AMPS;
```
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83746?usp=email
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Change subject: mb/google/brya/var/trulo: Remove mux references from typec port
......................................................................
mb/google/brya/var/trulo: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 1 insertion(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83746/2
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Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82682/comment/2dde4dd8_595e9a06?us… :
PS10, Line 17: confirm
It would be good if you share the method with test results on how value change verified.
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Change subject: mb/google/nissa: Add Vccin Aux Imon Iccmax default value for nissa/trulo
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 36:
(1 comment)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/711c3508_d298c4b6?us… :
PS30, Line 141: 0xfe02c000
> > why would FSP even bother to initialise the UART when we are setting UPD to PchSerialIoSkipInit to […]
we don't use FSP-T hence, ideally this is not applicable to us.
> Hi Subrata, yes, so to align the LPSS UART Base Addr b/w FSP and Coreboot, it would be good to have a UPD in FSP-M/S. We are working with FSP Team.
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