coreboot-gerrit August 2024

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[M] Change in coreboot[main]: [WIP] soc/amd/common/psp_smi: implement P2C mailbox handling
by Felix Held (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, ritul guru. Hello ritul guru, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83740?usp=email to review the following change. Change subject: [WIP] soc/amd/common/psp_smi: implement P2C mailbox handling ...................................................................... [WIP] soc/amd/common/psp_smi: implement P2C mailbox handling When the PSP wants to access the SPI flash during runtime, but isn't the owner of the SPI flash controller, it sends an SMI to the x86 side. The corresponding SMI handler then checks the P2C (PSP to core) mailbox for the command and data, processes the command, and if needed puts the requested data into the P2C buffer. The P2C mailbox is a memory region in TSEG aka SMM memory. Both location and size are communicated to the PSP via the PSP SMM info mailbox command which is sent right after mpinit is done. This commit adds the code to access the P2C mailbox to the PSP SMI handler code, but the handling of the actual mailbox commands the PSP sends to the SMI handler is added in later patches to keep the patch size manageable. This patch is a heavily reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. TODO: Check if all wbinvd calls are needed Test=TODO, but when selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Change-Id: I50479bed2332addae652026c6818460eeb6403af --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_smi.c M src/soc/amd/common/block/psp/psp_smm.c 3 files changed, 173 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83740/1 diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 72569ea..de4a6a0 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -120,4 +120,6 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value); +void enable_psp_smi(void); + #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_smi.c b/src/soc/amd/common/block/psp/psp_smi.c index b94366c..6f78d77 100644 --- a/src/soc/amd/common/block/psp/psp_smi.c +++ b/src/soc/amd/common/block/psp/psp_smi.c @@ -1,7 +1,177 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/psp.h> +#include <amdblocks/smi.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <device/mmio.h> +#include <types.h> +#include "psp_def.h" + +extern struct { + u8 buffer[P2C_BUFFER_MAXSIZE]; +} __aligned(32) p2c_buffer; + +static const uintptr_t p2c_mbox_base = (uintptr_t)&p2c_buffer.buffer; + +#define P2C_MBOX_COMMAND_OFFSET 0x00 +#define P2C_MBOX_STATUS_OFFSET 0x04 +#define P2C_MBOX_BUFFER_OFFSET 0x08 + +union p2c_mbox_status { + struct { + u32 checksum : 8; /* [ 0.. 7] */ + u32 checksum_en : 1; /* [ 8.. 8] */ + u32 reserved : 22; /* [ 9..30] */ + u32 command_ready : 1; /* [31..31] */ + }; + u32 raw; +}; + +/* PSP to x86 status */ +enum mbox_p2c_status { + MBOX_PSP_SUCCESS = 0x00, + MBOX_PSP_INVALID_PARAMETER = 0x01, + MBOX_PSP_CRC_ERROR = 0x02, + MBOX_PSP_COMMAND_PROCESS_ERROR = 0x04, + MBOX_PSP_UNSUPPORTED = 0x08, + MBOX_PSP_SPI_BUSY_ASYNC = 0x0a, + MBOX_PSP_SPI_BUSY = 0x0b, +}; + +static u8 rd_bios_mbox_checksum(void) +{ + union p2c_mbox_status tmp; + + tmp.raw = read32p(p2c_mbox_base + P2C_MBOX_STATUS_OFFSET); + return tmp.checksum; +} + +static void wr_bios_mbox_checksum(u8 checksum) +{ + union p2c_mbox_status tmp; + + tmp.raw = read32p(p2c_mbox_base + P2C_MBOX_STATUS_OFFSET); + tmp.checksum = checksum; + write32p(p2c_mbox_base + P2C_MBOX_STATUS_OFFSET, tmp.raw); +} + +static bool rd_bios_mbox_checksum_en(void) +{ + union p2c_mbox_status tmp; + + tmp.raw = read32p(p2c_mbox_base + P2C_MBOX_STATUS_OFFSET); + return !!tmp.checksum_en; +} + +static void wr_bios_mbox_ready(bool ready) +{ + union p2c_mbox_status tmp; + + tmp.raw = read32p(p2c_mbox_base + P2C_MBOX_STATUS_OFFSET); + tmp.command_ready = ready; + write32p(p2c_mbox_base + P2C_MBOX_STATUS_OFFSET, tmp.raw); +} + +void enable_psp_smi(void) +{ + wr_bios_mbox_ready(true); +} + +static void disable_psp_smi(void) +{ + wr_bios_mbox_ready(false); +} + +static void clear_psp_command(void) +{ + write32p(p2c_mbox_base + P2C_MBOX_COMMAND_OFFSET, 0); +} + +static u32 get_psp_command(void) +{ + return read32p(p2c_mbox_base + P2C_MBOX_COMMAND_OFFSET); +} + +static struct mbox_default_buffer *get_psp_command_buffer(void) +{ + return (struct mbox_default_buffer *)(p2c_mbox_base + P2C_MBOX_BUFFER_OFFSET); +} + +static uint32_t get_psp_cmd_buffer_length(void) +{ + return read32(&get_psp_command_buffer()->header.size); +} + +static u8 calc_psp_buffer_checksum8(void) +{ + const uint8_t *data = (const u8 *)get_psp_command_buffer(); + const size_t size = get_psp_cmd_buffer_length(); + u8 checksum = 0; + size_t i; + + for (i = 0; i < size; i++) + checksum += read8(data + i); + + return checksum; +} + +static void write_psp_cmd_buffer_status(uint32_t status) +{ + return write32(&get_psp_command_buffer()->header.status, status); +} + +static enum mbox_p2c_status check_psp_command(void) +{ + if (rd_bios_mbox_checksum_en() && + calc_psp_buffer_checksum8() != rd_bios_mbox_checksum()) + return MBOX_PSP_CRC_ERROR; + + if (get_psp_cmd_buffer_length() > P2C_BUFFER_MAXSIZE - P2C_MBOX_BUFFER_OFFSET) + return MBOX_PSP_INVALID_PARAMETER; + + return MBOX_PSP_SUCCESS; +} + +static void handle_psp_command(void) +{ + enum mbox_p2c_status status; + u32 cmd; + + status = check_psp_command(); + if (status != MBOX_PSP_SUCCESS) + goto out; + + cmd = get_psp_command(); + + switch (cmd) { + default: + printk(BIOS_ERR, "PSP: Unknown command %d\n", cmd); + status = MBOX_PSP_UNSUPPORTED; + break; + } + +out: + write_psp_cmd_buffer_status(status); + + if (status == MBOX_PSP_SUCCESS && rd_bios_mbox_checksum_en()) + wr_bios_mbox_checksum(calc_psp_buffer_checksum8()); +} void psp_smi_handler(void) { + disable_psp_smi(); + + wbinvd(); + + handle_psp_command(); + + wbinvd(); + + clear_psp_command(); + enable_psp_smi(); + + wbinvd(); + + reset_psp_smi(); } diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 4f76ebc..00e00dd 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -92,6 +92,7 @@ if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) { configure_psp_smi(); + enable_psp_smi(); } printk(BIOS_DEBUG, "PSP: Notify SMM info... "); -- To view, visit https://review.coreboot.org/c/coreboot/+/83740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50479bed2332addae652026c6818460eeb6403af Gerrit-Change-Number: 83740 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[M] Change in coreboot[main]: soc/amd: add PSP SMI handler stub
by Felix Held (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: ritul guru. Hello ritul guru, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83739?usp=email to review the following change. Change subject: soc/amd: add PSP SMI handler stub ...................................................................... soc/amd: add PSP SMI handler stub The PSP can send SMIs to the x86 side to have the SMI handler service requests from the PSP. This commit adds an empty PSP SMI handler; the actual implementation is added in later patches to keep the patches relatively small. This patch is a slightly modified version of parts of CB:65523. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.mk A src/soc/amd/common/block/psp/psp_smi.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/genoa_poc/smihandler.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/phoenix/smihandler.c M src/soc/amd/picasso/smihandler.c 11 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/83739/1 diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 2c5489f..fc59fd0 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -112,6 +112,9 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +#endif }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index abdb762..22b1efb 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -57,6 +57,8 @@ int psp_notify_smm(void); +void psp_smi_handler(void); + /* * type: identical to the corresponding PSP command, e.g. pass * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 266a6ba..c8bba89 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -88,6 +88,25 @@ Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is only available with NDA customers. +config SOC_AMD_COMMON_BLOCK_PSP_SMI + bool + default n + select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + Add PSP SMI handler for SPI flash access. + + When ROM armor isn't enabled, the x86 part owns the SPI controller, + so when the PSP wants to access the SPI flash, it sends an SMI to the + x86 side and the corresponding SMI handler will do the SPI flash + access for the PSP. + + WARNING: Since the flash access in the SMI handler is a blocking + operation during which all cores stay in SMM, an erase operation may + lock up the system for a long enough time to be noticable. Reads and + writes with small data sizes are less problematic. This is AMD + specific design and should be enabled when PSP requires to access the + SPI flash after the BOOT_DONE PSP command. + config PSP_INCLUDES_HSP bool depends on SOC_AMD_COMMON_BLOCK_PSP diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index d0fbcbe..c16a73b 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += psp.c ramstage-y += psp.c smm-y += psp.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi.c smm-y += psp_smm.c bootblock-y += psp_efs.c diff --git a/src/soc/amd/common/block/psp/psp_smi.c b/src/soc/amd/common/block/psp/psp_smi.c new file mode 100644 index 0000000..b94366c --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_smi.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/psp.h> + +void psp_smi_handler(void) +{ +} diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index f3b90ae..4f76ebc 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -6,6 +6,7 @@ #include <region_file.h> #include <console/console.h> #include <amdblocks/psp.h> +#include <amdblocks/smi.h> #include <soc/iomap.h> #include <string.h> @@ -89,6 +90,10 @@ soc_fill_smm_reg_info(&buffer.req.smm_reg_info); #endif + if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) { + configure_psp_smi(); + } + printk(BIOS_DEBUG, "PSP: Notify SMM info... "); cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SMM_INFO, &buffer); diff --git a/src/soc/amd/genoa_poc/smihandler.c b/src/soc/amd/genoa_poc/smihandler.c index a4b6173..5a6f5ee 100644 --- a/src/soc/amd/genoa_poc/smihandler.c +++ b/src/soc/amd/genoa_poc/smihandler.c @@ -81,6 +81,9 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +#endif }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/glinda/smihandler.c b/src/soc/amd/glinda/smihandler.c index 9cf754a..2c1bc72 100644 --- a/src/soc/amd/glinda/smihandler.c +++ b/src/soc/amd/glinda/smihandler.c @@ -112,6 +112,9 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +#endif }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/mendocino/smihandler.c b/src/soc/amd/mendocino/smihandler.c index a973658..5a587ca 100644 --- a/src/soc/amd/mendocino/smihandler.c +++ b/src/soc/amd/mendocino/smihandler.c @@ -112,6 +112,9 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +#endif }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/phoenix/smihandler.c b/src/soc/amd/phoenix/smihandler.c index a0099cf..ffdd858 100644 --- a/src/soc/amd/phoenix/smihandler.c +++ b/src/soc/amd/phoenix/smihandler.c @@ -112,6 +112,9 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +#endif }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 247a159..7295e9a 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -114,6 +114,9 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, +#endif }; void *get_smi_source_handler(int source) -- To view, visit https://review.coreboot.org/c/coreboot/+/83739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad Gerrit-Change-Number: 83739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com>

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[S] Change in coreboot[main]: commonlib/device_tree.c: Fix results length check
by Julius Werner (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Maximilian Brune, Paul Menzel. Julius Werner has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83085?usp=email ) Change subject: commonlib/device_tree.c: Fix results length check ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83085/comment/5ff6a64f_d4857306?us… : PS4, Line 11: > Paste the wrong warning and mention the board you saw this with? It's literally the warning that is getting modified by this patch? This code is not board-specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/83085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1111e8acb72ea1e9159da0d8386f40cbbdbc63f Gerrit-Change-Number: 83085 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 22:46:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE
by Matt DeVillier (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Sean Rhodes, Sergii Dmytruk. Matt DeVillier has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83737?usp=email ) Change subject: payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: this is already set for my repo via `payloads/external/edk2/Kconfig` ln 322, I'd just drop that conditional. or change that default to "" -- To view, visit https://review.coreboot.org/c/coreboot/+/83737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59f89c0f708f9b144bd35cd18870d0e1c65677d Gerrit-Change-Number: 83737 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 21:56:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: util/cbfstool: Rewrite trampoline in C
by Arthur Heymans (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Elyes Haouas, Martin L Roth, Paul Menzel. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63716?usp=email ) Change subject: util/cbfstool: Rewrite trampoline in C ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > Hey Arthur, this patch was looked at during the bi-weekly group review meeting and the comments came from the entire group. > > You marked the patch as RFC, which is why we commented. > > I don't think anyone was necessarily against this update, people were just pointing out possible issues - which are the same for every time we refactor working code or port something from pure ASM to inline ASM. There was a concern about the GCC team's choices for inline assembly which is where the comment came from. We rely on it pretty heavily at this point though, so if it's going to break here, it's likely to break elsewhere as well. > > > Making a 64bit version of this would trivial if it's compiled. Assembly would be pain. > I think this is a good argument for the switch, or at least for using this code for 64-bit booting. > > >> The ASM is well tested and doesn't really change much. > > Then the same would apply to a C version. > > The point of that comment was that ASM version has been around for over a decade. In a decade, the C version could say the same, but the longevity of the C version has not yet been stress tested. > > If this is a concern to people, we could use the C version for x64 until there's confidence and its use could be expanded to the full x86 platform. > Additionally, we can further vet the patch by looking at the output from a few generations of GCC to verify that the ASM output by the C version does the same thing as the ASM version. > > > Since you're not currently working on this, should it be marked WIP until you're ready to pick it up again? Updated it to work with framebuffer and more e820 entries like assembly. I'll try to test sometime. -- To view, visit https://review.coreboot.org/c/coreboot/+/63716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbd7a5ecd225edf87f451a82ff4cbe9fea522a89 Gerrit-Change-Number: 63716 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 01 Aug 2024 21:52:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: coreboot org <coreboot.org(a)gmail.com> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: vendorcode/intel: allow selecting EDK headers manually
by Sergii Dmytruk (Code Review) 01 Aug '24

01 Aug '24

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83738?usp=email ) Change subject: vendorcode/intel: allow selecting EDK headers manually ...................................................................... vendorcode/intel: allow selecting EDK headers manually EFI-specific options depend on CONFIG_UDK_BASE which gets set by CONFIG_*_BINDING selected by SOCs. This prevents enabling those options for boards which don't require EDK bindings. Make version of the bindings freely selectable when SOC doesn't request a specific version and EDK2 payload is used. This looks somewhat ugly and duplicated because otherwise kconfig will detect a loop in configuration options and refuse to do anything. Change-Id: I964142ef64967b4c9b329025ebcad701e34a5035 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.mk 2 files changed, 44 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83738/1 diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 69fbc00..7d34308 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -23,6 +23,41 @@ def_bool n select UDK_BASE +# The version is user-configurable only if SOC didn't requests a specific one. +# In that case, it can be useful to have these headers to enable EFI-specific +# options when EDK2 payload is in use. +if !UEFI_2_4_BINDING && \ + !UDK_2017_BINDING && \ + !UDK_202005_BINDING && \ + !UDK_202111_BINDING && \ + !UDK_202302_BINDING && \ + PAYLOAD_EDK2 + +choice + prompt "Set of UEFI headers to use" + +config USE_NO_UEFI_BINDING + bool "None" +config USE_UEFI_2_4_BINDING + bool "UEFI 2.4" + select UDK_BASE +config USE_UDK_2017_BINDING + bool "UDK 2017" + select UDK_BASE +config USE_UDK_202005_BINDING + bool "UDK 202005" + select UDK_BASE +config USE_UDK_202111_BINDING + bool "UDK 202111" + select UDK_BASE +config USE_UDK_202302_BINDING + bool "UDK 202302" + select UDK_BASE + +endchoice + +endif + if UDK_BASE config UDK_2013_VERSION int @@ -46,10 +81,10 @@ config UDK_VERSION int - default 202302 if UDK_202302_BINDING - default 202111 if UDK_202111_BINDING - default 202005 if UDK_202005_BINDING - default 2017 if UDK_2017_BINDING + default 202302 if UDK_202302_BINDING || USE_UDK_202302_BINDING + default 202111 if UDK_202111_BINDING || USE_UDK_202111_BINDING + default 202005 if UDK_202005_BINDING || USE_UDK_202005_BINDING + default 2017 if UDK_2017_BINDING || USE_UDK_2017_BINDING default 2013 help UEFI Development Kit version for Platform diff --git a/src/vendorcode/intel/Makefile.mk b/src/vendorcode/intel/Makefile.mk index 67c7210..6aea9ad 100644 --- a/src/vendorcode/intel/Makefile.mk +++ b/src/vendorcode/intel/Makefile.mk @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_UEFI_2_4_BINDING),y) +ifeq ($(CONFIG_UEFI_2_4_BINDING)$(CONFIG_USE_UEFI_2_4_BINDING),y) # ProccessorBind.h provided in Ia32 directory. Types are derived from ia32. # It's possible to provide our own ProcessorBind.h using posix types. However, # ProcessorBind.h isn't just about types. There's compiler definitions as well @@ -9,24 +9,24 @@ CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include -else ifeq ($(CONFIG_UDK_2017_BINDING),y) +else ifeq ($(CONFIG_UDK_2017_BINDING)$(CONFIG_USE_UDK_2017_BINDING),y) CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32 CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdeModulePkg/Include -else ifeq ($(CONFIG_UDK_202005_BINDING),y) +else ifeq ($(CONFIG_UDK_202005_BINDING)$(CONFIG_USE_UDK_202005_BINDING),y) CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32 CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdeModulePkg/Include -else ifeq ($(CONFIG_UDK_202111_BINDING),y) +else ifeq ($(CONFIG_UDK_202111_BINDING)$(CONFIG_USE_UDK_202111_BINDING),y) CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32 CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include -else ifeq ($(CONFIG_UDK_202302_BINDING),y) +else ifeq ($(CONFIG_UDK_202302_BINDING)$(CONFIG_USE_UDK_202302_BINDING),y) CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32 CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include -- To view, visit https://review.coreboot.org/c/coreboot/+/83738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I964142ef64967b4c9b329025ebcad701e34a5035 Gerrit-Change-Number: 83738 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[XS] Change in coreboot[main]: payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE
by Sergii Dmytruk (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes. Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83737?usp=email ) Change subject: payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE ...................................................................... payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE Official EDK2 repository has VARIABLE_SUPPORT defaulting to EMU in UefiPayloadPkg, switch it to SMMSTORE if coreboot is built with it. Change-Id: Ic59f89c0f708f9b144bd35cd18870d0e1c65677d Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M payloads/external/Makefile.mk M payloads/external/edk2/Makefile 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/83737/1 diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 53693f5..a0f1f31 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -189,6 +189,7 @@ CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=$(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS) \ CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \ + CONFIG_SMMSTORE=$(CONFIG_SMMSTORE) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \ CONFIG_EDK2_SECURE_BOOT_SUPPORT=$(CONFIG_EDK2_SECURE_BOOT_SUPPORT) \ CONFIG_EDK2_GOP_DRIVER=$(CONFIG_EDK2_GOP_DRIVER) \ @@ -238,6 +239,7 @@ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \ + CONFIG_SMMSTORE=$(CONFIG_SMMSTORE) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 3966b91..c493012 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -69,6 +69,10 @@ ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE endif +# VARIABLE_SUPPORT = EMU +ifeq ($(CONFIG_SMMSTORE),y) +BUILD_STR += -D VARIABLE_SUPPORT=SMMSTORE +endif # MAX_VARIABLE_SIZE = 0x10000 ifeq ($(CONFIG_SMMSTORE_V2),y) BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize=0x8000 -- To view, visit https://review.coreboot.org/c/coreboot/+/83737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59f89c0f708f9b144bd35cd18870d0e1c65677d Gerrit-Change-Number: 83737 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[L] Change in coreboot[main]: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules
by Sergii Dmytruk (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Krystian Hebel, Patrick Rudolph. Hello Krystian Hebel, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83422?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules ...................................................................... drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules How it approximately works: (During a normal system run): 1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI runtime 2. If applying the update requires a reboot, EFI implementation creates a new CapsuleUpdateData* EFI variable pointing at the beginning of capsules description (not data, but description of the data) and does a warm reboot leaving capsule data and its description in RAM to be picked by firmware on the next boot process (After DEV_INIT:) 3. Capsules are discovered by checking for CapsuleUpdateData* variables 4. Capsule description in memory and capsule data is validated for sanity 5. Capsule data is coalesced into a continuous piece of memory (On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:) 6. Buffer with coalesced capsules is marked as reserved (On BS_WRITE_TABLES via lb_uefi_capsules() hook:) 7. coreboot table entry is added for each of the discovered capsules (In UEFI payload:) 8. CapsuleUpdateData* get removed 9. coreboot table is checked for any update capsules which are then applied Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/efi/Kconfig M src/drivers/efi/Makefile.mk A src/drivers/efi/capsules.c A src/drivers/efi/capsules.h M src/include/boot/coreboot_tables.h M src/lib/bootmem.c M src/lib/coreboot_table.c M src/security/memory/memory_clear.c 9 files changed, 815 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83422/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Gerrit-Change-Number: 83422 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[XS] Change in coreboot[main]: payloads/edk2: configure capsule updates
by Sergii Dmytruk (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Benjamin Doron, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes. Hello Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83682?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: payloads/edk2: configure capsule updates ...................................................................... payloads/edk2: configure capsule updates This requires version of EDK2 in use to understand those defines, but the build isn't affected negatively if they aren't handled. Upstream EDK2 already has CAPSULE_SUPPORT although it won't enable FMP capsules. Change-Id: I1c684cb8929842a5d3c4b06e8a9c0a748470ea41 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M payloads/external/Makefile.mk M payloads/external/edk2/Makefile 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/83682/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c684cb8929842a5d3c4b06e8a9c0a748470ea41 Gerrit-Change-Number: 83682 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[L] Change in coreboot[main]: util/cbfstool: Rewrite trampoline in C
by Arthur Heymans (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Elyes Haouas, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63716?usp=email to look at the new patch set (#6). Change subject: util/cbfstool: Rewrite trampoline in C ...................................................................... util/cbfstool: Rewrite trampoline in C Rewrite the trampoline in C code. Now it does use stack that is set up at a reasonable offset above the entry point. As a bonus the trampoline can now check the payload argument instead of searching for "LBIO" in lower memory. Works on QEMU q35: tested both with calling argument containing a pointer to lb_header as with searching lower memory. Change-Id: Ibbd7a5ecd225edf87f451a82ff4cbe9fea522a89 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/Makefile D util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c A util/cbfstool/x86_linux_trampoline.c 4 files changed, 269 insertions(+), 225 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63716/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbd7a5ecd225edf87f451a82ff4cbe9fea522a89 Gerrit-Change-Number: 63716 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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