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Change subject: superio/ite/it8728f: Support setting power state after power failure
......................................................................
Patch Set 5: Code-Review+2
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Change subject: Makefiles: Download 3rdparty/chromeec when needed
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Abandoned
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Change subject: [IT'S A PAIN - plan to deprecate ?] chromeec submodule
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
chromeec submodule is gone. This can be abandoned.
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Change subject: mb/lattepanda: Add support for LattePanda Mu
......................................................................
Patch Set 5:
(3 comments)
Patchset:
PS5:
Just a couple of small changes and I think it can be merged.
Thanks!
Commit Message:
https://review.coreboot.org/c/coreboot/+/83719/comment/e6ce97a0_54036b8f?us… :
PS5, Line 27: Power on after shutdown: Failed (requires power removal)
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
File src/mainboard/lattepanda/mu/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/83719/comment/c214baac_c7238905?us… :
PS5, Line 8:
Nit: remove extra line
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: libpayload: Add missing SIZE_MAX define
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
This actually goes, strangely enough, into <stdint.h>, even though the type is defined in <stddef.h>: https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/stdint.h.html#tag…
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Change subject: mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
would be good if you can test this on your v1.0 board
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Change subject: mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration
......................................................................
mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration
Looking at Intel document 759603 revision 001, Alder Lake N only has 5
PCIe clock outputs and clock request pins. I only have the version 2 of
this board which has a significantly different USB port configuration to
version 1, but there the Ethernet controller on RP 11 and the E key m.2
slot on RP 12 share the last PCIe clock output. The on-board TUBF0304
clock buffer chip takes the clock output form the last PCH PCIe clock
generator output and drives the clock inputs of both the last Ethernet
chip and the E key m.2 slot. Since the last clock output is always
active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the
non-existent clock output and request for RP 12 didn't break things.
ASPM L0s might still work though, since that one doesn't involve
switching off the PCIe reference clock, but haven't tested that yet.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378
---
M src/mainboard/cwwk/adl/devicetree.cb
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/83911/1
diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb
index 0963d8f..7dd95d7 100644
--- a/src/mainboard/cwwk/adl/devicetree.cb
+++ b/src/mainboard/cwwk/adl/devicetree.cb
@@ -42,9 +42,9 @@
}"
register "pch_pcie_rp[PCH_RP(12)]" = "{
- .clk_src = 5,
- .clk_req = 5,
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ .clk_src = 4,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+ .pcie_rp_aspm = ASPM_DISABLE,
}"
# Enable EDP in PortA
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Change subject: mb/cwwk/adl/devicetree: enable all USB ports
......................................................................
mb/cwwk/adl/devicetree: enable all USB ports
The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on
the mainboard and likely also routes one USB2 port to the m.2 E key slot
which is typically used for Bluetooth support when an E key m.2 WIFI +
Bluetooth card is installed.
This is untested, since I only have the cw-al-4l-v2.0 mainboard, but
from looking at the documentation of the version 1 and looking at how
things are done on the version 2 this should be correct.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d
---
M src/mainboard/cwwk/adl/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/83910/1
diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb
index 15ec3b2..0963d8f 100644
--- a/src/mainboard/cwwk/adl/devicetree.cb
+++ b/src/mainboard/cwwk/adl/devicetree.cb
@@ -6,7 +6,10 @@
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"
+ register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"
+ register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader
+ register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)"
register "pch_pcie_rp[PCH_RP(1)]" = "{
.clk_src = 0,
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