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Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,109 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/80
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Saurabh Mishra has uploaded a new patch set (#39) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/dptf.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 2,004 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/39
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Karthik Ramasubramanian has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/83905?usp=email )
Change subject: mb/google/dedede/var/awasuki: Enable HECI 1
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possible
......................................................................
Patch Set 2: Code-Review+2
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Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83908?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possible
......................................................................
soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possible
Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)'
which is a helper function that does exactly the same, but slightly
simplifies the call.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83908/2
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83908?usp=email )
Change subject: soc/intel/xeon_sp_uncore_acpi: use is_dev_on_domain0 where possible
......................................................................
soc/intel/xeon_sp_uncore_acpi: use is_dev_on_domain0 where possible
Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)'
which is a helper function that does exactly the same, but slightly
simplifies the call.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83908/1
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 0b2b9f4..baffdd0 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -532,7 +532,7 @@
struct device *dev = NULL;
struct device *iommu0 = NULL;
while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
- if (is_domain0(dev_get_domain(dev))) {
+ if (is_dev_on_domain0(dev)) {
iommu0 = dev;
continue;
}
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Attention is currently required from: Alexander Couzens, Angel Pons, Felix Singer, Michał Kopeć, Paul Menzel.
Maciej Pijanowski has posted comments on this change by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email )
Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
Jan,
I went ahead and removed these comments as requested, that should resolve most (if not all) comments.
It was just very tedious to do to remove some comments from automatically generated file.
Note that this was not tested, so if you are willing to help, that would be great. Also if there are some more changes needed here, feel free to jump in if needed.
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