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Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83064?usp=email )
Change subject: cpu/x86/smm: Add save state ops for different save states
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS4:
> Hey Arthur, Is this currently being worked?
I not currently. The series probably needs to be updated to account for the fact that synchronous SMI can not be differentiated in qemu. Other than that I need to address the comments.
File src/cpu/x86/smm/legacy_save_state.c:
https://review.coreboot.org/c/coreboot/+/83064/comment/0fae86b9_e63ca5e4?us… :
PS4, Line 89: }
> This looks like it would go wrong 1 out of 512 times on a dual core / socket system.
> Is there no way to detect the AMPC or did just nobody look into it?
There is apparently but it depends on the hardware whether the 'I/O State Field' exists.
"Processors that have an SMM revision ID of 30004H or higher have the incremental state information described below."
I think using CPU registers for this interface was a mistake. Finding which cpu initiated the synchronous SMI does not always go right iirc (I think the workaround is to try multiple times). There used to be a SMIF in GNVS for this purpose.
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Change subject: [RFC]soc/intel/cannonlake: Use regular NEM for CAR
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Change subject: [RFC] drivers/amd/agesa/state_machine: disable NULL breakpoint for binaryPI
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Change subject: include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74619/comment/22e5f8df_8f907fe6?us… :
PS1, Line 17: .
> Doh!
Done
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Hello build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74619?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by coreboot org
Change subject: include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
......................................................................
include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since
it was defined as unsigned long in AGESA.h, a workaround was needed in
cpu/amd/mtrr.h to not have the build fail due to a non-identical
redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround
without reaming the defines isn't trivially possible, since the
stoneyridge romstage.c still ends up including both definitions which
can't be easily worked around. Now all non-vendorcode coreboot code uses
TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and
TOP_MEM2 to avoid this.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455
---
M src/drivers/amd/agesa/s3_mtrr.c
M src/include/cpu/amd/mtrr.h
2 files changed, 6 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/74619/2
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Attention is currently required from: Angel Pons, Felix Singer, Julius Werner, Lean Sheng Tan, Maximilian Brune, Nico Huber.
Hello Angel Pons, Felix Singer, Julius Werner, Lean Sheng Tan, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83615?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: util/cbfstool/cbfs-payload-linux: Do not compress bzImage
......................................................................
util/cbfstool/cbfs-payload-linux: Do not compress bzImage
Compressing the already compressed bzImage does not yield any
fruit. If you are lucky it actually makes the image a little bit
smaller. If you are unlucky the image actually gets bigger and since the
compressing function is not checked for any errors, coreboot just builds
successfully even though the payload is broken through compression.
Before this patch you could possibly get this error during compilation:
```
E: LZMA: LzmaEnc_Encode failed 9.
```
and your linux payload would end up something like this in CBFS:
```
FMAP REGION: COREBOOT
Name Offset Type Size Comp
....
fallback/payload 0x1c9c0 simple elf 511 none
....
```
That doesn't stop coreboot from finishing the build though, since we
currently don't check for errors from the compression. That is an issue
for another patch though.
Tested:
Build and run QEMU-Q35 with Linux bzImage as payload.
Change-Id: I022982667515ce721d98af534414d9e336b5f35a
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M util/cbfstool/cbfs-payload-linux.c
1 file changed, 24 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83615/6
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