Attention is currently required from: Weimin Wu.
Hello Weimin Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83906?usp=email
to look at the new patch set (#3).
Change subject: mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz
......................................................................
mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz
Before:
I2C4 - 413KHz
After:
I2C4 - 370KHz
BUG=b:351968527
TEST=Rate of the actual measured machine is 370KHz
Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Signed-off-by: Wei Hualin <weihualin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/83906/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/83906?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Gerrit-Change-Number: 83906
Gerrit-PatchSet: 3
Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83865?usp=email )
Change subject: soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
......................................................................
soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:
Found overlapped clkreq assignment on clk req 0
Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file
Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 10 insertions(+), 6 deletions(-)
Approvals:
Maximilian Brune: Looks good to me, approved
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index d917e6c..a63b64c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -71,10 +71,12 @@
printk(BIOS_WARNING, "Missing root port clock structure definition\n");
continue;
}
- if (clk_req_mapping & (1 << cfg[i].clk_req))
- printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
- , cfg[i].clk_req);
+
if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
+ if (clk_req_mapping & (1 << cfg[i].clk_req))
+ printk(BIOS_WARNING,
+ "Found overlapped clkreq assignment on clk req %d\n",
+ cfg[i].clk_req);
m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
clk_req_mapping |= 1 << cfg[i].clk_req;
}
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 9734c63..055fec7 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -52,10 +52,12 @@
printk(BIOS_WARNING, "Missing root port clock structure definition\n");
continue;
}
- if (clk_req_mapping & (1 << cfg[i].clk_req))
- printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
- , cfg[i].clk_req);
+
if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
+ if (clk_req_mapping & (1 << cfg[i].clk_req))
+ printk(BIOS_WARNING,
+ "Found overlapped clkreq assignment on clk req %d\n",
+ cfg[i].clk_req);
m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
clk_req_mapping |= 1 << cfg[i].clk_req;
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/83865?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Gerrit-Change-Number: 83865
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun <tstuli(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83906?usp=email
to look at the new patch set (#2).
Change subject: mb/google/dedede/var/awasuki: Modify rate 0f i2c speed
......................................................................
mb/google/dedede/var/awasuki: Modify rate 0f i2c speed
Set the I2C4 rate to 370KHz
BUG=b:351968527
TEST=Rate of the actual measured machine is 370KHz
Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Signed-off-by: Wei Hualin <weihualin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/83906/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/83906?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Gerrit-Change-Number: 83906
Gerrit-PatchSet: 2
Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83635?usp=email
to look at the new patch set (#77).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,130 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/77
--
To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Gerrit-Change-Number: 83635
Gerrit-PatchSet: 77
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Attention is currently required from: Dinesh Gehlot, Eric Lai, Jakub Czapiga.
Subrata Banik has posted comments on this change by Jakub Czapiga. ( https://review.coreboot.org/c/coreboot/+/83907?usp=email )
Change subject: libpayload: Add missing SIZE_MAX define
......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/83907?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I588d59c2637b10def046ea02293e5503c9b6bc3d
Gerrit-Change-Number: 83907
Gerrit-PatchSet: 3
Gerrit-Owner: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Eric Lai <ericllai(a)google.com>
Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Comment-Date: Wed, 14 Aug 2024 12:48:07 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Attention is currently required from: Dinesh Gehlot, Eric Lai, Subrata Banik.
Jakub Czapiga has posted comments on this change by Jakub Czapiga. ( https://review.coreboot.org/c/coreboot/+/83907?usp=email )
Change subject: libpayload: Add missing SIZE_MAX define
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Added safeguard for case when compiler does not define `__SIZE_MAX__`
--
To view, visit https://review.coreboot.org/c/coreboot/+/83907?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I588d59c2637b10def046ea02293e5503c9b6bc3d
Gerrit-Change-Number: 83907
Gerrit-PatchSet: 3
Gerrit-Owner: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Eric Lai <ericllai(a)google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Comment-Date: Wed, 14 Aug 2024 12:43:04 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No