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Change subject: mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-up
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83904/comment/b5cb8d9c_de66456b?us… :
PS1, Line 9: Due to internal pull-up resistor of 65Kohm in /RST pin in GT7986U(Touch Controller, we will change GPP_C1 from PP&internal pull-up to OD&no pull-up in PCH GPIO Table.
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
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Change subject: mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-up
......................................................................
mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-up
EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table.
BUG=b:358472598
TEST=Build and verified test result by EE team
Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f
Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/sundance/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83904/2
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Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83792/comment/3fd5d93f_07de0af6?us… :
PS3, Line 8:
> > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […]
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
......................................................................
mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
This patch removes WWAN configuration from the bootblock.
It appears that setting it up in the bootblock may not be necessary.
Configure in bootblock,the seq will be triggered at the same time.
The customer would like us to leave some buffer for EN to RST.
BUG=b:357764679
TEST=Build and verified test result by EE team
Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/sundance/gpio.c
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83792/6
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Change subject: mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz
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Patch Set 3: Code-Review+1
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 38:
(4 comments)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/4225cd5a_5d6575d8?us… :
PS17, Line 38: GPP_ASPIO
> I have changed GPP_ASPI0 to GPP_A in other places.
Done
https://review.coreboot.org/c/coreboot/+/83789/comment/bb55eedd_ecd18472?us… :
PS17, Line 73: .num_groups = ARRAY_SIZE(ptl_community0_groups),
> in progress. Some further check needed. […]
Subrata, Same as cpu_port. I'd like to know your opinion on this due to the 16-bit port id changes needed for this.
https://review.coreboot.org/c/coreboot/+/83789/comment/a7c677d5_edd2bef0?us… :
PS17, Line 177: { PMC_GPP_E, GPP_E },
> sure. will make the changes.
Done
File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/83789/comment/5a29f525_9976d35e?us… :
PS17, Line 544: #define GPP_VGPIO0 246
> in progress.
The response is that these are for internal only and there is no plan to provide VGPIO info in EDS.
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Change subject: soc/intel/common/systemagent: Improve systemagent
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
Can you split this into 2? Define optional registers, add soc fixup?
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
......................................................................
mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
This patch removes WWAN configuration from the bootblock.
It appears that setting it up in the bootblock may not be necessary.
If we configure in bootblock,the seq will be triggered at the same time.
The customer would like us to leave some buffer for EN to RST.
BUG=b:357764679
TEST=Build and verified test result by EE team
Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/sundance/gpio.c
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83792/5
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Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
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Patch Set 80: -Code-Review
(1 comment)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/4ef43de0_5fbe6073?us… :
PS80, Line 225: default 3 if SOC_INTEL_DEBUG_CONSENT
> This is not a critical thing, so we can make changes later but I'd like to suggest to set the default value to 4 if SOC_INTEL_DEBUG_CONSENT is enabled and update the help comments to align with fsp header file.
please get this fix before we land this CL.
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