coreboot-gerrit August 2024

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[S] Change in coreboot[main]: [Prepare for C23]nb/amd/pi
by Elyes Haouas (Code Review) 15 Aug '24

15 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83916?usp=email ) Change subject: [Prepare for C23]nb/amd/pi ...................................................................... [Prepare for C23]nb/amd/pi Modern C provides nullptr constant. Prepare to use it unstead of macro. Change-Id: I6cb809d8f043c3003d60752dbcf0f22f0130288e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/pcengines/apu2/OemCustomize.c M src/northbridge/amd/pi/00730F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/pci.c 5 files changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/83916/1 diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 95af6ef..c47b12b 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -71,7 +71,7 @@ .Flags = DESCRIPTOR_TERMINATE_LIST, .SocketId = 0, .PciePortList = PortList, - .DdiLinkList = NULL, + .DdiLinkList = nullptr, }; void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index c24466e..0108f3e 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -16,12 +16,12 @@ int spdAddress; DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); - if (dev == NULL) + if (dev == nullptr) return AGESA_ERROR; DEVTREE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info; - if (config == NULL) + if (config == nullptr) return AGESA_ERROR; if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 1be9421..f315cd4 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -98,11 +98,11 @@ current = (void *)(hest + 1); addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) + if (addr != nullptr) current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) + if (addr != nullptr) current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); return (unsigned long)current; @@ -270,7 +270,7 @@ /* * These devices should be already found by previous function. - * Do not perform NULL checks. + * Do not perform nullptr checks. */ struct device *nb_dev = pcidev_on_root(0, 0); struct device *iommu_dev = pcidev_on_root(0, 2); @@ -313,7 +313,7 @@ current_backup = current; current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); ivhd_11->length += (current - current_backup); - add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivhd_11->length); + add_ivhd_device_entries(nullptr, all_devices, 0, -1, nullptr, &current, &ivhd_11->length); /* Describe HPET */ current_backup = current; @@ -350,7 +350,7 @@ } ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs_agesa != NULL) { + if (ivrs_agesa != nullptr) { ivrs->iv_info = ivrs_agesa->iv_info; ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; @@ -368,7 +368,7 @@ if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) ivrs->iv_info |= IVINFO_EFR_SUPPORTED; } else { - printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); + printk(BIOS_WARNING, "%s: AGESA returned nullptr IVRS\n", __func__); return (unsigned long)ivrs; } @@ -381,7 +381,7 @@ current_backup = current; current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); ivrs->ivhd.length += (current - current_backup); - add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); + add_ivhd_device_entries(nullptr, all_devices, 0, -1, nullptr, &current, &ivrs->ivhd.length); /* Describe HPET */ current_backup = current; @@ -447,40 +447,40 @@ current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); - if (srat != NULL) { + if (srat != nullptr) { memcpy((void *)current, srat, srat->header.length); srat = (acpi_srat_t *)current; current += srat->header.length; acpi_add_table(rsdp, srat); } else { - printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SRAT table nullptr. Skipping.\n"); } /* SLIT */ current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); - if (slit != NULL) { + if (slit != nullptr) { memcpy((void *)current, slit, slit->header.length); slit = (acpi_slit_t *)current; current += slit->header.length; acpi_add_table(rsdp, slit); } else { - printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SLIT table nullptr. Skipping.\n"); } /* ALIB */ current = ALIGN_UP(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); - if (alib != NULL) { + if (alib != nullptr) { memcpy((void *)current, alib, alib->length); alib = (acpi_header_t *)current; current += alib->length; acpi_add_table(rsdp, (void *)alib); } else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA ALIB SSDT table nullptr. Skipping.\n"); } /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ @@ -488,13 +488,13 @@ current = ALIGN_UP(current, 16); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); - if (ssdt != NULL) { + if (ssdt != nullptr) { memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *)current; current += ssdt->length; } else { - printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA PState table nullptr. Skipping.\n"); } acpi_add_table(rsdp, ssdt); @@ -547,7 +547,7 @@ /* disable No Snoop */ dev = pcidev_on_root(1, 1); - if (dev != NULL) { + if (dev != nullptr) { pci_and_config32(dev, 0x60, ~(1 << 11)); } } @@ -647,7 +647,7 @@ if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0"; - return NULL; + return nullptr; } struct device_operations amd_fam16_mod30_pci_domain_ops = { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 66ec824..4538454 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -317,12 +317,12 @@ static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) - return NULL; + return nullptr; if (dev->path.pci.devfn == LPC_DEVFN) return "LIBR"; - return NULL; + return nullptr; } static void lpc_final(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index b99413c..33ffe5d 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -24,7 +24,7 @@ * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, nullptr); static struct pci_operations lops_pci = { .set_subsystem = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/83916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cb809d8f043c3003d60752dbcf0f22f0130288e Gerrit-Change-Number: 83916 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Saurabh Mishra (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... Patch Set 80: (1 comment) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83635/comment/4925b4ef_84a21e9e?us… : PS80, Line 225: default 3 if SOC_INTEL_DEBUG_CONSENT > > This is not a critical thing, so we can make changes later but I'd like to suggest to set the defa […] Ack, fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 80 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 15 Aug 2024 06:01:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Saurabh Mishra (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83635?usp=email to look at the new patch set (#81). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/chip.h A src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/include/soc/gpe.h A src/soc/intel/pantherlake/include/soc/meminit.h A src/soc/intel/pantherlake/include/soc/msr.h A src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/romstage.h A src/soc/intel/pantherlake/include/soc/soc_chip.h A src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/meminit.c A src/soc/intel/pantherlake/reset.c A src/soc/intel/pantherlake/romstage/Makefile.mk A src/soc/intel/pantherlake/romstage/fsp_params.c A src/soc/intel/pantherlake/romstage/romstage.c A src/soc/intel/pantherlake/romstage/systemagent.c 17 files changed, 1,113 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/81 -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 81 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
by Dinesh Gehlot (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Felix Held, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Roger Wang, Shou-Chieh Hsu. Dinesh Gehlot has posted comments on this change by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/83792?usp=email ) Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Gerrit-Change-Number: 83792 Gerrit-PatchSet: 6 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Aug 2024 05:47:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: [Prepare for C23]i945: Use nullptr instead of NULL
by Elyes Haouas (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev. Hello Alexander Couzens, Evgeny Zinoviev, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83860?usp=email to look at the new patch set (#4). Change subject: [Prepare for C23]i945: Use nullptr instead of NULL ...................................................................... [Prepare for C23]i945: Use nullptr instead of NULL Modern C provides nullptr constant. Prepare to use it unstead of macro. Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/mptable.c M src/mainboard/getac/p470/mptable.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/intel/d945gclf/mptable.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/roda/rk886ex/mptable.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c 14 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83860/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5 Gerrit-Change-Number: 83860 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[XS] Change in coreboot[main]: [test C23 i945]: Use nullptr instead of NULL
by Elyes Haouas (Code Review) 15 Aug '24

15 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83915?usp=email ) Change subject: [test C23 i945]: Use nullptr instead of NULL ...................................................................... [test C23 i945]: Use nullptr instead of NULL Change-Id: I7f3c203645ba325573d8dd6939022c253bdbd5e5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83915/1 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 32eff1a..12187b6 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -10,6 +10,7 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select USE_DDR2 select NEED_SMALL_2MB_PAGE_TABLES + select ALLOW_UNSUPPORTED_C23 if NORTHBRIDGE_INTEL_I945 -- To view, visit https://review.coreboot.org/c/coreboot/+/83915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f3c203645ba325573d8dd6939022c253bdbd5e5 Gerrit-Change-Number: 83915 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: [C23] i945: Use nullptr instead of NULL
by Elyes Haouas (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev. Hello Alexander Couzens, Evgeny Zinoviev, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83860?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [C23] i945: Use nullptr instead of NULL ...................................................................... [C23] i945: Use nullptr instead of NULL Modern C provides nullptr constant. Prepare to use it unstead of macro. Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/mptable.c M src/mainboard/getac/p470/mptable.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/intel/d945gclf/mptable.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/roda/rk886ex/mptable.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c 14 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83860/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5 Gerrit-Change-Number: 83860 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[XS] Change in coreboot[main]: mb/google/brya/var/nova: Set up soundbar-related gpios
by Eric Lai (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Kenneth Chan, Nick Vaccaro, Rishika Raj, Subrata Banik. Eric Lai has posted comments on this change by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/83878?usp=email ) Change subject: mb/google/brya/var/nova: Set up soundbar-related gpios ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/nova/gpio.c: https://review.coreboot.org/c/coreboot/+/83878/comment/f3b70ba6_62c314bf?us… : PS5, Line 44: PAD_CFG_GPO > Done Lock the pin still can change the output value. -- To view, visit https://review.coreboot.org/c/coreboot/+/83878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49815aa3e3192e98170861c4d168c8136def5ccd Gerrit-Change-Number: 83878 Gerrit-PatchSet: 5 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Aug 2024 05:23:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz
by Eric Lai (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Subrata Banik, hualin wei. Eric Lai has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/83906?usp=email ) Change subject: mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Why change the max not the parameter? -- To view, visit https://review.coreboot.org/c/coreboot/+/83906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c Gerrit-Change-Number: 83906 Gerrit-PatchSet: 3 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 15 Aug 2024 05:21:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: commonlib/bsd/string: Fix pointer overflow for strnlen()
by Mario Scheithauer (Code Review) 15 Aug '24

15 Aug '24

Attention is currently required from: Jakub Czapiga, Maximilian Brune, Yu-Ping Wu. Mario Scheithauer has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83914?usp=email ) Change subject: commonlib/bsd/string: Fix pointer overflow for strnlen() ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Looks good. I have tested it on mc_ehl1 mainboard and it works again. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/83914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9d983b11391f5e05c2bceb262682aced5206f94 Gerrit-Change-Number: 83914 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 15 Aug 2024 05:07:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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