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Change subject: commonlib/bsd/string: Fix pointer overflow for strnlen()
......................................................................
Patch Set 1:
(1 comment)
File src/commonlib/bsd/string.c:
https://review.coreboot.org/c/coreboot/+/83914/comment/9b5feddc_34eb4f35?us… :
PS1, Line 19: str + maxlen + 1
> edit: sorry, that was supposed to be `MIN()`, of course. Actually, neither of those is great. Hmmm.. […]
That's algorithmically incorrect in some edge cases, for example when `str = UINTPTR_MAX` and `maxlen = 1`. I've considered different ways to write the code, but all of them don't seem to be better than the counter approach.
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Subrata Banik has posted comments on this change by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/83878?usp=email )
Change subject: mb/google/brya/var/nova: Set up soundbar-related gpios
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/nova/gpio.c:
https://review.coreboot.org/c/coreboot/+/83878/comment/b337cf18_c8fef8b0?us… :
PS5, Line 44: PAD_CFG_GPO
> Lock the pin still can change the output value.
lock is like locking the pad configuration and not the Tx/Rx. Hence, I would suggest to locking the PIN if you don;t need to reconfigure this PAD after booting to OS.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83898?usp=email )
Change subject: soc/intel/alderlake: Correct ISH partition availability check
......................................................................
soc/intel/alderlake: Correct ISH partition availability check
The previous implementation incorrectly assumed that the presence of a
UFS device implied the availability of the ISH partition. This is not
always true, especially on Alder Lake platforms where ISH may be
enabled by default even without UFS.
This patch fixes the issue by directly checking for the presence of the
ISH device to determine if the ISH partition is available.
BUG=b:359440547
TEST=1. Able to dump the ISH version with UFS device:
```
tirwen-rev3 ~ # cbmem -c -1 | grep ISH
[DEBUG] ISH version: 5.4.2.7780
```
2. Able to dump the ISH version with eMMC device:
```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.7780
```
Change-Id: I411e36606c0697f91050af40e0636f7c64810e95
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/soc/intel/alderlake/chip.c
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Dinesh Gehlot: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 45fb39f..8979ae0f6 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -167,16 +167,16 @@
/*
* SoC override API to identify if ISH Firmware existed inside CSE FPT.
*
- * SoC with UFS enabled would like to keep ISH enabled as well, hence
- * identifying the UFS enabled device is enough to conclude that the ISH
- * partition also is available.
+ * Identifying the ISH enabled device is required to conclude that the ISH
+ * partition also is available (because ISH may be default enabled for non-UFS
+ * platforms as well starting with Alder Lake).
*/
bool soc_is_ish_partition_enabled(void)
{
- struct device *ufs = pcidev_path_on_root(PCH_DEVFN_UFS);
- uint16_t ufs_pci_id = ufs ? pci_read_config16(ufs, PCI_DEVICE_ID) : 0xFFFF;
+ struct device *ish = pcidev_path_on_root(PCH_DEVFN_ISH);
+ uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF;
- if (ufs_pci_id == 0xFFFF)
+ if (ish_pci_id == 0xFFFF)
return false;
return true;
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Attention is currently required from: Karthik Ramasubramanian, hualin wei.
Subrata Banik has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/83906?usp=email )
Change subject: mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83906/comment/54c75609_638621b7?us… :
PS3, Line 38: I2C_SPEED_FAST - 30000
should follow the defined template as per I2C spec. If the controller doesn't support fast speed, please use the standard aka 100KHz
```
enum i2c_speed {
I2C_SPEED_STANDARD = 100000,
I2C_SPEED_FAST = 400000,
I2C_SPEED_FAST_PLUS = 1000000,
I2C_SPEED_HIGH = 3400000,
I2C_SPEED_FAST_ULTRA = 5000000,
};
```
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Attention is currently required from: Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Subrata Banik.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83635?usp=email
to look at the new patch set (#82).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,113 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/82
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Attention is currently required from: Michał Żygowski, Piotr Król.
Hello Michał Żygowski, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83916?usp=email
to look at the new patch set (#2).
Change subject: [Prepare for C23]nb/amd/pi: Use nullptr instead of NULL
......................................................................
[Prepare for C23]nb/amd/pi: Use nullptr instead of NULL
Modern C provides nullptr constant. Prepare to use it unstead of macro.
Change-Id: I6cb809d8f043c3003d60752dbcf0f22f0130288e
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/mainboard/pcengines/apu2/OemCustomize.c
M src/northbridge/amd/pi/00730F01/dimmSpd.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
5 files changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/83916/2
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