coreboot-gerrit July 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
by Patrick Rudolph (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82252?usp=email ) Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Gerrit-Change-Number: 82252 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 14:34:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/common/smi_util: add PSP SMI helper functions
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, ritul guru. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83702?usp=email to look at the new patch set (#3). Change subject: soc/amd/common/smi_util: add PSP SMI helper functions ...................................................................... soc/amd/common/smi_util: add PSP SMI helper functions The PSP can send SMIs to the x86 side of the system. Add helper functions to configure and to reset the PSP SMI generation. Since Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific smi.h to bring it in line with the newer SoCs. This patch is split out from CB:65523. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf --- M src/soc/amd/common/block/include/amdblocks/smi.h M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/stoneyridge/include/soc/smi.h 3 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/83702/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83702?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf Gerrit-Change-Number: 83702 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: device/path: rename domain path struct element to 'domain_id'
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83677?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device/path: rename domain path struct element to 'domain_id' ...................................................................... device/path: rename domain path struct element to 'domain_id' Rename the 'domain' element of the 'domain_path' struct to 'domain_id' to clarify that this element is the domain ID. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_const.c M src/device/device_util.c M src/include/device/path.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/spr/ioat.c M util/sconfig/main.c 6 files changed, 9 insertions(+), 9 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/device/device_const.c b/src/device/device_const.c index fc76304..9f3443e 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -118,7 +118,7 @@ equal = (path1->apic.apic_id == path2->apic.apic_id); break; case DEVICE_PATH_DOMAIN: - equal = (path1->domain.domain == path2->domain.domain); + equal = (path1->domain.domain_id == path2->domain.domain_id); break; case DEVICE_PATH_CPU_CLUSTER: equal = (path1->cpu_cluster.cluster diff --git a/src/device/device_util.c b/src/device/device_util.c index 22dc5f7..3514de7 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -109,7 +109,7 @@ ret |= dev->path.apic.apic_id; break; case DEVICE_PATH_DOMAIN: - ret |= dev->path.domain.domain; + ret |= dev->path.domain.domain_id; break; case DEVICE_PATH_CPU_CLUSTER: ret |= dev->path.cpu_cluster.cluster; @@ -193,7 +193,7 @@ break; case DEVICE_PATH_DOMAIN: snprintf(buffer, sizeof(buffer), "DOMAIN: %08x", - dev->path.domain.domain); + dev->path.domain.domain_id); break; case DEVICE_PATH_CPU_CLUSTER: snprintf(buffer, sizeof(buffer), "CPU_CLUSTER: %01x", @@ -273,12 +273,12 @@ return 0; } - return domain_dev->path.domain.domain; + return domain_dev->path.domain.domain_id; } bool is_domain0(const struct device *dev) { - return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain == 0; + return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain_id == 0; } bool is_dev_on_domain0(const struct device *dev) diff --git a/src/include/device/path.h b/src/include/device/path.h index f8c4390..d8ef880 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -53,7 +53,7 @@ } struct domain_path { - unsigned int domain; + unsigned int domain_id; }; struct pci_path { diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 4731bec..ed278a3 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -30,7 +30,7 @@ .bus = bus, }; path->type = DEVICE_PATH_DOMAIN; - path->domain.domain = dp.domain_path; + path->domain.domain_id = dp.domain_path; }; /* diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 8b9921a..fcc3a20 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -44,7 +44,7 @@ struct device_path path = { .type = DEVICE_PATH_DOMAIN, .domain = { - .domain = new_path.domain_path, + .domain_id = new_path.domain_path, }, }; struct device *const domain = alloc_find_dev(upstream, &path); diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 9acd592..acab06a 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -859,7 +859,7 @@ break; case DOMAIN: - new_d->path = ".type=DEVICE_PATH_DOMAIN,{.domain={ .domain = 0x%x }}"; + new_d->path = ".type=DEVICE_PATH_DOMAIN,{.domain={ .domain_id = 0x%x }}"; break; case GENERIC: -- To view, visit https://review.coreboot.org/c/coreboot/+/83677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Gerrit-Change-Number: 83677 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: device: introduce and use dev_get_domain_id
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83644?usp=email ) Change subject: device: introduce and use dev_get_domain_id ...................................................................... device: introduce and use dev_get_domain_id To avoid having constructs like 'dev->path.domain.domain' in the SoC code, create the 'dev_get_domain_id' helper function that returns the domain ID of either that device if it's a domain device or the corresponding domain device's domain ID, and use it in the code. If this function is called with a device other than PCI or domain type, it won't have a domain number. In order to not need to call 'die', 'dev_get_domain_id' will print an error and return 0 which is a valid domain number. In that case, the calling code should be fixed. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/device_util.c M src/include/device/device.h M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/data_fabric/pci_segment_multi.c M src/soc/amd/common/block/data_fabric/pci_segment_single.c M src/soc/amd/common/block/root_complex/root_complex.c M src/soc/amd/genoa_poc/domain.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 12 files changed, 31 insertions(+), 14 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/device/device_util.c b/src/device/device_util.c index 2e97ece..22dc5f7 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <commonlib/bsd/helpers.h> #include <console/console.h> #include <device/device.h> @@ -261,6 +262,20 @@ return NULL; } +unsigned int dev_get_domain_id(const struct device *dev) +{ + const struct device *domain_dev = dev_get_domain(dev); + + assert(domain_dev); + + if (!domain_dev) { + printk(BIOS_ERR, "%s: doesn't have a domain device\n", dev_path(dev)); + return 0; + } + + return domain_dev->path.domain.domain; +} + bool is_domain0(const struct device *dev) { return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain == 0; diff --git a/src/include/device/device.h b/src/include/device/device.h index ac8a117..3eee321 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -183,6 +183,7 @@ const char *dev_path(const struct device *dev); u32 dev_path_encode(const struct device *dev); const struct device *dev_get_domain(const struct device *dev); +unsigned int dev_get_domain_id(const struct device *dev); void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); bool dev_is_active_bridge(struct device *dev); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index c419fe0..12a7bba 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -22,7 +22,7 @@ if (segment_group >= PCI_SEGMENT_GROUP_COUNT) { printk(BIOS_ERR, "Skipping domain %u due to too large segment group %u.\n", - domain->path.domain.domain, segment_group); + dev_get_domain_id(domain), segment_group); return; } diff --git a/src/soc/amd/common/block/data_fabric/pci_segment_multi.c b/src/soc/amd/common/block/data_fabric/pci_segment_multi.c index bc680f9..433b004 100644 --- a/src/soc/amd/common/block/data_fabric/pci_segment_multi.c +++ b/src/soc/amd/common/block/data_fabric/pci_segment_multi.c @@ -29,6 +29,6 @@ } printk(BIOS_ERR, "No valid DF PCI CFG register pair found for domain %x.\n", - domain->path.domain.domain); + dev_get_domain_id(domain)); return CB_ERR; } diff --git a/src/soc/amd/common/block/data_fabric/pci_segment_single.c b/src/soc/amd/common/block/data_fabric/pci_segment_single.c index 3e02d96..49e6b9a 100644 --- a/src/soc/amd/common/block/data_fabric/pci_segment_single.c +++ b/src/soc/amd/common/block/data_fabric/pci_segment_single.c @@ -27,6 +27,6 @@ } printk(BIOS_ERR, "No valid DF PCI CFG register found for domain %x.\n", - domain->path.domain.domain); + dev_get_domain_id(domain)); return CB_ERR; } diff --git a/src/soc/amd/common/block/root_complex/root_complex.c b/src/soc/amd/common/block/root_complex/root_complex.c index 2bcdc1d..72eba8a 100644 --- a/src/soc/amd/common/block/root_complex/root_complex.c +++ b/src/soc/amd/common/block/root_complex/root_complex.c @@ -7,7 +7,7 @@ static const struct domain_iohc_info *get_domain_iohc_info(struct device *domain) { - const unsigned int domain_id = domain->path.domain.domain; + const unsigned int domain_id = dev_get_domain_id(domain); const struct domain_iohc_info *iohc; size_t iohc_count; diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 88f386c..b6369a4 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -26,7 +26,7 @@ { if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n", - domain->path.domain.domain); + dev_get_domain_id(domain)); const union df_vga_en vga_en = { .ve = 1, .dst_fabric_id = get_iohc_fabric_id(domain), @@ -48,6 +48,7 @@ static const char *genoa_domain_acpi_name(const struct device *domain) { + const unsigned int domain_id = dev_get_domain_id(domain); const char *domain_acpi_names[4] = { "S0B0", "S0B1", @@ -55,8 +56,8 @@ "S0B3", }; - if (domain->path.domain.domain < ARRAY_SIZE(domain_acpi_names)) - return domain_acpi_names[domain->path.domain.domain]; + if (domain_id < ARRAY_SIZE(domain_acpi_names)) + return domain_acpi_names[domain_id]; return NULL; } diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index f66f5e9..e5cf907 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -95,7 +95,7 @@ void iio_domain_set_acpi_name(struct device *dev, const char *prefix) { const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain + .domain_path = dev_get_domain_id(dev) }; assert(dn.socket < CONFIG_MAX_SOCKET); diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index d0eab02..011e1c3 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -49,7 +49,7 @@ return 0; union xeon_domain_path dn; - dn.domain_path = domain->path.domain.domain; + dn.domain_path = dev_get_domain_id(domain); if (socket != XEONSP_SOCKET_MAX && dn.socket != socket) return 0; @@ -140,7 +140,7 @@ if (!domain) return -1; - dn.domain_path = domain->path.domain.domain; + dn.domain_path = dev_get_domain_id(domain); return dn.socket; } @@ -162,7 +162,7 @@ if (!domain) return -1; - dn.domain_path = domain->path.domain.domain; + dn.domain_path = dev_get_domain_id(domain); return dn.stack; } diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index a68c764..ee167e2 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -17,7 +17,7 @@ { assert(dev->path.type == DEVICE_PATH_DOMAIN); const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain + .domain_path = dev_get_domain_id(dev) }; const IIO_UDS *hob = get_iio_uds(); diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index 686b3e4..d53b231 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -16,7 +16,7 @@ { assert(dev->path.type == DEVICE_PATH_DOMAIN); const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain + .domain_path = dev_get_domain_id(dev) }; const IIO_UDS *hob = get_iio_uds(); diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 609ac55..b371034 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -128,7 +128,7 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev) { static uint32_t slot_num; - const uint32_t domain = dev->upstream->dev->path.domain.domain; + const uint32_t domain = dev_get_domain_id(dev); const uint32_t devfn = dev->path.pci.devfn; const struct vendorcode_amd_opensil_chip_mpio_config *const config = dev->chip_info; printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/83644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Gerrit-Change-Number: 83644 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Felix Singer, Martin Roth, Maxim. Felix Held has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83018?usp=email ) Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: looks like this patch needs a manual rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/83018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6889ad8ad861465316333ff997956a05b74c5855 Gerrit-Change-Number: 83018 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 14:30:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/superiotool/fintek: Add f81966 register table
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83019?usp=email ) Change subject: util/superiotool/fintek: Add f81966 register table ...................................................................... util/superiotool/fintek: Add f81966 register table In accordance with the F81962/F81964/F81966/F81967 datasheet: Release Date: Feb, 2018, Version: V0.18P [1]. [1] https://web.archive.org/web/20240707052102/http:// www.jetwaycomputer.com/download/Fintek/F81966_wdt_gpio.zip Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 157 insertions(+), 2 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 390e8e3..3abcc57 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -10,10 +10,10 @@ #define FINTEK_VENDOR_ID 0x3419 -/* f81866 Port Select (27h): BANK_PROG_SEL[3-2] CLK_TUNE_PROG_EN[0] */ +/* f81866 f81966 Port Select (27h): BANK_PROG_SEL[3-2] CLK_TUNE_PROG_EN[0] */ #define ESEL_27H(bank, en) {.name = "Port Select Register", .idx = 0x27, .mask = 0x0d, \ .val = esel_27h_##bank | esel_27h_clk_tune_##en} -/* f81866 Fan Fault Time Register (9Fh): FAN_PROG_SEL[7] */ +/* f81866 f81966 Fan Fault Time Register (9Fh): FAN_PROG_SEL[7] */ #define ESEL_9FH(bank) {.name = "Fan Fault Time Register", .idx = 0x9f, .mask = 0x80, \ .val = esel_9fh_fan_prog_##bank} /* f81866 Block Write Count Register (ECh) ECh: MCH_BANK_SEL[7] */ @@ -565,6 +565,105 @@ {NANA, 0x00, 0x00, NANA, NANA, 0x04, NANA, 0x00, 0x00, 0x00, EOT}}, {EOT}}}, {0x0215, "F81962/F81964/F81966/F81967", { + {NOLDN, "Global", + {0x02, 0x07, 0x20, 0x21, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, + 0x2a, 0x2b, 0x2c, 0x2d, EOT}, + {NANA, 0x00, 0x15, 0x02, 0x19, 0x34, 0x00, 0x23, 0x02, 0xa0, 0x00, + 0x00, 0x02, 0x0c, 0x28, EOT}, + ESEL_27H(bank0, dis)}, /* selectable */ + {NOLDN, "Global", + {0x27, 0x28, 0x2a, 0x2b, 0x2c, EOT}, + {0x02, 0x00, 0x00, 0x00, 0x00, EOT}, + ESEL_27H(bank1, dis)}, /* selectable */ + {NOLDN, "Global", + {0x27, 0x28, 0x2a, 0x2b, 0x2c, EOT}, + {0x02, 0x03, 0x60, 0x00, 0x00, EOT}, + ESEL_27H(bank2, dis)}, /* selectable */ + {NOLDN, "Global", + {0x27, 0x28, 0x2a, 0x2b, 0x2c, EOT}, + {0x02, 0x5b, 0x03, 0x00, 0x18, EOT}, + ESEL_27H(bank3, dis)}, /* selectable */ + {NOLDN, "Global", + {0x27, 0x29, 0x2c, 0x2b, 0x2c, EOT}, + {0x02, 0x03, 0xe7, NANA, 0x00, EOT}, + ESEL_27H(bank0, en)}, /* selectable */ + {0x03, "LPT", + {0x30, 0x60, 0x61, 0x70, 0x74, 0xf0, EOT}, + {NANA, 0x03, 0x78, 0x07, 0x03, 0xc2, EOT}}, + {0x04, "HWMON", + {0x30, 0x60, 0x61, 0x70, EOT}, + {NANA, 0x02, 0x95, NANA, EOT}}, + {0x05, "KBC", + {0x30, 0x60, 0x61, 0x70, 0x72, 0xfe, EOT}, + {NANA, 0x00, 0x60, NANA, NANA, 0x00, EOT}}, + {0x06, "GPIO", + {0x30, 0x60, 0x61, 0x70, 0x71, 0x72, 0x73, 0x7e, 0x7f, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, /* f0...f8 GPIO0 */ + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, /* e0...e6 GPIO1 */ + 0xd0, 0xd1, 0xd2, /* d0...d2 GPIO2 */ + 0xc0, 0xc1, 0xc2, 0xc3, /* c0...c3 GPIO3 */ + 0xb0, 0xb1, 0xb2, 0xb3, /* b0...b3 GPIO4 */ + 0xa0, 0xa1, 0xa2, 0xa4, 0xa5, 0xa6, /* a0...c6 GPIO5 */ + 0x90, 0x91, 0x92, 0x93, /* 90...93 GPIO6 */ + 0x80, 0x81, 0x82, 0x83, /* 80...83 GPIO7 */ + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, /* 88...8e GPIO8 */ + 0x98, 0x99, 0x9a, 0x9b, /* 98...9b GPIO9 */ + EOT}, + {NANA, 0x00, 0x60, NANA, NANA, NANA, NANA, 0x00, 0x00, + 0x00, 0x0f, NANA, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, /* f0...f8 GPIO0 */ + 0x00, 0xff, NANA, 0x00, 0x00, 0xff, 0x00, /* e0...e6 GPIO1 */ + 0x00, 0xff, NANA, /* d0...d2 GPIO2 */ + 0x00, 0xff, NANA, 0x00, /* c0...c3 GPIO3 */ + 0x00, 0xff, NANA, 0x00, /* b0...b3 GPIO4 */ + 0x00, 0xff, NANA, 0x00, 0xff, 0x00, /* a0...c6 GPIO5 */ + 0x00, 0xff, NANA, 0x00, /* 90...93 GPIO6 */ + 0x00, 0xff, NANA, 0x00, /* 80...83 GPIO7 */ + 0x00, 0xff, NANA, 0x00, 0x00, 0xff, 0x00, /* 88...8e GPIO8 */ + 0x00, 0xff, NANA, 0x00, /* 98...9b GPIO9 */ + EOT}}, + {0x07, "WDT", + {0x30, 0x60, 0x61, 0xf0, 0xf5, 0xf6, 0xfa, EOT}, + {NANA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, EOT}}, + {0x0a, "PME, ACPI & ERP", + {0x30, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, + 0xec, 0xed, 0xee, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf8, + 0xf9, 0xfa, 0xfc, 0xfd, 0xfe, EOT}, + {NANA, 0x00, 0x0c, 0x8c, 0x13, 0x09, 0xc7, 0x09, 0x63, 0x00, 0x0f, + 0x14, 0x00, 0x00, 0x00, NANA, 0x00, NANA, 0x07, 0x1c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x00, 0x00, EOT}}, + {0x0f, "SPI Master", + {0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, EOT}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x03, EOT}}, + {0x10, "UART1", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xfe, 0xff, EOT}, + {NANA, 0x03, 0xf8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xff, EOT}}, + {0x11, "UART2", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xfe, 0xff, EOT}, + {NANA, 0x02, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xff, EOT}}, + {0x12, "UART3", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xfe, 0xff, EOT}, + {NANA, 0x03, 0xe8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xff, EOT}}, + {0x13, "UART4", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xfe, 0xff, EOT}, + {NANA, 0x02, 0xe8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xff, EOT}}, + {0x14, "UART5", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xfe, 0xff, EOT}, + {NANA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xff, EOT}}, + {0x15, "UART6", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xfe, 0xff, EOT}, + {NANA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xff, EOT}}, {EOT}}}, {EOT} }; @@ -687,6 +786,62 @@ {0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, {EOT}}}, + {0x0215, "F81804/F81962/F81964/F81966/F81967", { + {NOLDN, "General", /* 5.4.6 Hardware Monitor General Setting & 5.4.13 PECI/TSI/I2C Setting */ + {0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, + 0x0d, 0x0e, 0x0f, EOT}, + {0x03, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x4c, 0x00, 0x00, 0x00, 0x55, + 0x00, 0x00, 0x02, EOT}}, + {NOLDN, "PECI Command", /* 5.4.22 PECI Command Setting */ + {0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, + 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, EOT}, + {0x44, 0x00, NANA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, EOT}}, + {NOLDN, "TSI/MXM", /* 5.4.39 TSI/MXM Temperature */ + {0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, + 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, EOT}, + {NANA, NANA, NANA, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, NANA, 0x01, 0x00, EOT}}, + {NOLDN, "Temperature Monitor", /* 5.4.56 Temperature Related Register */ + {0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c, 0x6d, 0x6f, 0x7f, + 0x72, 0x74, 0x7a, 0x7b, 0x7e, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, + EOT}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x44, 0x04, NANA, 0x00, + NANA, NANA, NANA, NANA, NANA, 0x46, 0x3c, 0x64, 0x55, 0x64, 0x55, + EOT}}, + {NOLDN, "Voltage Monitor", /* 5.4.69 Voltage Setting */ + {0x10, 0x11, 0x12, 0x14, 0x15, 0x16, 0x17, 0x20, 0x21, 0x22, 0x23, + 0x24, 0x25, 0x26, 0x27, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3f, EOT}, + {0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, NANA, NANA, NANA, NANA, + NANA, NANA, NANA, NANA, NANA, NANA, NANA, 0x89, 0xf2, 0xe2, 0xe1, + 0x83, 0x96, 0xff, 0x00, EOT}}, + {NOLDN, "FAN Control", /* 5.4.79 General Fan Control Setting */ + {0x90, 0x91, 0x92, 0x93, 0x94, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, + 0x9c, 0x9d, 0x9e, 0x9f, EOT}, + {0x00, NANA, NANA, 0x00, 0x00, 0x15, 0x00, 0x44, 0x02, 0x00, 0x15, + 0x55, 0x05, 0x66, 0x0a, EOT}, + ESEL_9FH(bank0)}, /* selectable */ + {NOLDN, "FAN Control", + {0x94, 0x95, 0x96, 0x97, 0x9a, 0x9b, EOT}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x15, EOT}, + ESEL_9FH(bank1)}, /* selectable */ + {NOLDN, "FAN1 Monitor", /* 5.4.101 FAN1 Control Register */ + {0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, + 0xab, 0xac, 0xad, 0xae, 0xaf, EOT}, + {0x0f, 0xff, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, + 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, + {NOLDN, "FAN2 Monitor", /* 5.4.101 FAN1 Control Register */ + {0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, + 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, EOT}, + {0x0f, 0xff, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, + 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, + {NOLDN, "FAN3 Monitor", /* 5.4.101 FAN1 Control Register */ + {0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, + 0xcb, 0xcc, 0xcd, 0xce, 0xcf, EOT}, + {0x0f, 0xff, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, + 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, + {EOT}}}, {EOT} }; -- To view, visit https://review.coreboot.org/c/coreboot/+/83019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Gerrit-Change-Number: 83019 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: util/superiotool/fintek: Add f81866 register table
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83004?usp=email ) Change subject: util/superiotool/fintek: Add f81866 register table ...................................................................... util/superiotool/fintek: Add f81866 register table In accordance with the F81866A datasheet: Release Date: Jan, 2012, Version: V0.14P [1]. [1] https://web.archive.org/web/20240707051837/http://www. jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83004 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/superiotool/fintek.c 1 file changed, 179 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 035ec5f..390e8e3 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -10,6 +10,37 @@ #define FINTEK_VENDOR_ID 0x3419 +/* f81866 Port Select (27h): BANK_PROG_SEL[3-2] CLK_TUNE_PROG_EN[0] */ +#define ESEL_27H(bank, en) {.name = "Port Select Register", .idx = 0x27, .mask = 0x0d, \ + .val = esel_27h_##bank | esel_27h_clk_tune_##en} +/* f81866 Fan Fault Time Register (9Fh): FAN_PROG_SEL[7] */ +#define ESEL_9FH(bank) {.name = "Fan Fault Time Register", .idx = 0x9f, .mask = 0x80, \ + .val = esel_9fh_fan_prog_##bank} +/* f81866 Block Write Count Register (ECh) ECh: MCH_BANK_SEL[7] */ +#define ESEL_ECH(data_temp) {.name = "Block Write Count Register", .idx = 0xec, .mask = 0x80, \ + .val = esel_ech_mch_bank_##data_temp} + +enum esel_27h_bank_prog_sel { + esel_27h_bank0 = 0 << 2, + esel_27h_bank1 = 1 << 2, + esel_27h_bank2 = 2 << 2, + esel_27h_bank3 = 3 << 2, +}; +enum esel_27h_clk_tune { + esel_27h_clk_tune_dis = 0, + esel_27h_clk_tune_en = 1, +}; + +enum esel_9fh_fan_prog { + esel_9fh_fan_prog_bank0 = 0 << 7, + esel_9fh_fan_prog_bank1 = 1 << 7, +}; + +enum esel_ech_mch_bank { + esel_ech_mch_bank_temp = 0 << 7, + esel_ech_mch_bank_data = 1 << 7, +}; + static const struct superio_registers reg_table[] = { {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */ /* We assume reserved bits are read as 0. */ @@ -450,6 +481,88 @@ {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, {EOT}}}, {0x1010, "F81866", { + {NOLDN, NULL, /* Global Control Registers */ + {0x02, 0x07, 0x20, 0x21, 0x23, 0x24, 0x25, 0x26, 0x27, 0x2d, EOT}, + {NANA, 0x00, 0x10, 0x10, 0x19, 0x34, 0x00, 0x03, 0x00, 0x08, EOT}}, + {NOLDN, NULL, + {0x27, 0x2d, 0x28, 0x29, 0x2a, 0x2b, 0x2c, EOT}, + {0x00, 0x08, 0x60, 0x03, NANA, 0x02, NANA, EOT}, + ESEL_27H(bank0, dis)}, /* selectable */ + {NOLDN, NULL, + {0x27, 0x28, 0x2c, EOT}, + {0x00, NANA, 0x0f, EOT}, + ESEL_27H(bank1, dis)}, /* selectable */ + {NOLDN, NULL, + {0x27, 0x2c, EOT}, + {0x00, 0x00, EOT}, + ESEL_27H(bank2, dis)}, /* selectable */ + {NOLDN, NULL, + {0x27, 0x29, 0x2A, 0x2b, 0x2c, EOT}, + {0x00, 0x03, 0xe7, NANA, NANA, EOT}, + ESEL_27H(bank0, en)}, /* selectable */ + {0x00, "FDC", + {0x30, 0x60, 0x61, 0x70, 0x74, 0xf0, 0xf2, 0xf4, EOT}, + {NANA, 0x03, 0xf0, NANA, NANA, NANA, NANA, NANA, EOT}}, + {0x03, "LPT", + {0x30, 0x60, 0x61, 0x70, 0x74, 0xf0, EOT}, + {NANA, 0x03, 0x78, NANA, NANA, NANA, EOT}}, + {0x04, "HWMON", + {0x30, 0x60, 0x61, 0x70, EOT}, + {NANA, 0x02, 0x95, NANA, EOT}}, + {0x05, "KBC", + {0x30, 0x60, 0x61, 0x70, 0x72, 0xfe, EOT}, + {NANA, 0x00, 0x60, NANA, NANA, NANA, EOT}}, + {0x06, "GPIO", + {0x30, 0x60, 0x61, 0x70, 0x71, 0x72, 0x73, 0x7e, 0x7f, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, /* f0...f9 GPIO0 */ + 0xe0, 0xe1, 0xe2, 0xe3, 0xe8, 0xe9, /* e0...e9 GPIO1 */ + 0xd0, 0xd1, 0xd2, 0xd3, /* d0...d3 GPIO2 */ + 0xc0, 0xc1, 0xc2, 0xc3, /* c0...c3 GPIO3 */ + 0xb0, 0xb1, 0xb2, 0xb3, /* b0...b3 GPIO4 */ + 0xa0, 0xa1, 0xa2, 0xa3, 0xa8,0xa9, /* a0...a9 GPIO5 */ + 0x90, 0x91, 0x92, 0x93, /* 90...93 GPIO6 */ + 0x80, 0x81, 0x82, 0x83, /* 80...83 GPIO7 */ + 0x88, 0x89, 0x8a, 0x8b, 0x8e, 0x8f, /* 88...8f GPIO8 */ + EOT}, + {NANA, 0x00, 0x60, NANA, NANA, NANA, NANA, 0x00, 0x00, + 0x00, 0x0f, NANA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* f0...f9 GPIO0 */ + 0x00, 0xff, NANA, 0x00, 0x00, 0x00, /* e0...e9 GPIO1 */ + 0x00, 0xff, NANA, 0x00, /* d0...d3 GPIO2 */ + 0x00, 0xff, NANA, 0x00, /* c0...c3 GPIO3 */ + 0x00, 0xff, NANA, 0x00, /* b0...b3 GPIO4 */ + 0x00, 0xff, NANA, 0x00, 0x00, 0x00, /* a0...a9 GPIO5 */ + 0x00, 0xff, NANA, 0x00, /* 90...93 GPIO6 */ + 0x00, 0xff, NANA, 0x00, /* 80...83 GPIO7 */ + 0x00, 0xff, NANA, 0x00, 0x00, 0x00, /* 88...8f GPIO8 */ + EOT}}, + {0x07, "WDT", + {0x30, 0x60, 0x61, 0xf5, 0xf6, 0xfa, EOT}, + {NANA, 0x00, 0x00, 0x00, 0x00, NANA, EOT}}, + {0x0a, "PME, ACPI & ERP", + {0x30, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf8, 0xf9, 0xfa, + 0xfc, 0xfe, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, + 0xe9, 0xec, 0xed, 0xee, EOT}, + {NANA, 0x00, NANA, 0x00, NANA, 0x07, 0x1c, 0x00, 0x00, 0x00, 0x07, + 0x00, 0x00, 0x0c, 0x00, 0x00, 0x13, 0x09, 0xc7, 0x13, 0x63, 0x10, + 0x0f, 0x14, 0x00, 0x00, EOT}}, + {0x10, "UART1", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT}, + {NANA, 0x03, 0xf8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}}, + {0x11, "UART2", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT}, + {NANA, 0x02, 0xf8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}}, + {0x12, "UART3", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT}, + {NANA, 0x03, 0xe8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}}, + {0x13, "UART4", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT}, + {NANA, 0x02, 0xe8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}}, + {0x14, "UART5", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT}, + {NANA, 0x00, 0x00, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}}, + {0x15, "UART6", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf1, 0xf2, 0xf4, 0xf5, 0xf6, EOT}, + {NANA, 0x00, 0x00, NANA, NANA, 0x04, NANA, 0x00, 0x00, 0x00, EOT}}, {EOT}}}, {0x0215, "F81962/F81964/F81966/F81967", { {EOT}}}, @@ -508,6 +621,72 @@ NANA, NANA, NANA, NANA, NANA, 0x00, 0x01, 0x01, 0x00, EOT}}, {EOT}}}, + {0x1010, "F81866", { + /* 6.4.2.1 Configuration Setting */ + {NOLDN, "General", + {0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0f, 0xe0, + 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xec, 0xed, + 0xee, 0xef, EOT}, + {0x03, 0x00, 0x00, 0x4c, 0x00, 0x10, 0x00, 0x55, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, + 0x01, 0x00, EOT}}, + {NOLDN, "TSI/I2C", + {0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xec, 0xed, + 0xee, 0xef, EOT}, + {NANA, NANA, NANA, NANA, NANA, NANA, NANA, NANA, NANA, 0x00, 0x00, + 0x01, 0x00, EOT}, + ESEL_ECH(temp)}, /* selectable */ + /* 6.4.2.3 PECI 3.0 & Temperature Setting */ + {NOLDN, "PECI", + {0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, + 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, EOT}, + {0x00, 0x00, RSVD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, EOT}}, + {NOLDN, "Temperature Monitor", + {0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c, 0x6d, 0x6f, 0x70, + 0x72, 0x73, 0x74, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x80, 0x81, 0x82, + 0x83, 0x84, 0x85, 0x7f, 0x8e, EOT}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x44, 0x04, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x64, 0x55, 0x64, + 0x55, 0x64, 0x55, 0x00, 0xaa, EOT}}, + /* 6.4.2.4 Voltage Setting */ + {NOLDN, "Voltage Monitor", + {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x3f, 0x20, 0x21, + 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x2d, 0x2e, 0x2f, 0x30, 0x31, + 0x36, 0x37, 0x38, 0x39, 0x3a, EOT}, + {0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x89, 0xf2, + 0xe2, 0xe1, 0x83, 0x96, 0xff, EOT}}, + {NOLDN, "FAN Control", /* 6.4.2.5 Fan Control Setting - Control Setting */ + {0x90, 0x91, 0x92, 0x93, 0x97, 0x98, 0x99, 0x9a, 0x9c, 0x9d, 0x9e, + 0x9f, EOT}, + {0x00, RSVD, RSVD, 0x00, 0x00, 0x44, 0x02, 0x00, 0x55, 0x05, 0x66, + 0x0a, EOT}, + }, + {NOLDN, "FAN Control", + {0x94, 0x95, 0x96, 0x9b, 0x9f, EOT}, + {0x00, NANA, 0x19, 0x19, 0x0a, EOT}, + ESEL_9FH(bank0)}, /* selectable */ + {NOLDN, "FAN Control", + {0x94, 0x95, 0x96, 0x9b, 0x9f, EOT}, + {0x00, 0x00, 0x00, 0x19, 0x0a, EOT}, + ESEL_9FH(bank1)}, /* selectable */ + {NOLDN, "FAN1 Monitor", /* 6.4.2.5 Fan Control Setting - FAN 1,2,3 */ + {0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, + 0xab, 0xac, 0xad, 0xae, 0xaf, EOT}, + {0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, + 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, + {NOLDN, "FAN2 Monitor", + {0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, + 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, EOT}, + {0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, + 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, + {NOLDN, "FAN3 Monitor", + {0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, + 0xcb, 0xcc, 0xcd, 0xce, 0xcf, EOT}, + {0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff, + 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}}, + {EOT}}}, {EOT} }; -- To view, visit https://review.coreboot.org/c/coreboot/+/83004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Gerrit-Change-Number: 83004 Gerrit-PatchSet: 19 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: util/superiotool: Add extra selectors support
by Felix Held (Code Review) 31 Jul '24

31 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83196?usp=email ) Change subject: util/superiotool: Add extra selectors support ...................................................................... util/superiotool: Add extra selectors support Some chips (fintek [1,2]) have registers with specific selector-fields that can affect the address space of the device (for example, switch the register bank). At the same time, these registers contain fields that should not change after they are configured in BIOS (for example, set the port to 2E/2F or 4E/4F). In this case, the selector should take into account the mask of the register fields and there is no convenient and easy way to add this in the code in the utility. The selector-fields should be set manually before the dump and this action is done several times. This patch adds an extra-selector mechanism that allows superiotool to make a correct dump in automatic mode. Just add a structure with an index, mask, and value for the selector inside the superio_registers chip for the corresponding LDN to switch the register bank: {FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", { * * * {NOLDN, "Global", {0x28,0x2a,0x2b,0x2c,EOT}, {0x00,0x00,0x00,0x00,EOT}, {.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */ }, {0x03, "LPT", {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, {NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */ }, * * * Tested with Fintek F81966 on Asrock IMB-1222: - run superiotool on Ubuntu and dump the registers for the board with the vendor's firmware; - add the superio chip initialization code to the board configuration in coreboot and build the project; - boot Ubuntu on the board with coreboot and re-dump the registers; - the register values from the board configuration code are the same in both dumps. Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e (Global) -- ESEL[27h] 0x00 (Port Select Register) -- idx 02 07 20 21 23 24 25 26 27 28 29 2a 2b 2c 2d val 00 0b 15 02 19 34 5a 23 80 a0 f0 45 02 e3 2e def NA 00 15 02 19 34 00 23 02 a0 00 00 02 0c 28 * * * The changes do not affect the configuration of existing chips, which was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D (the dump before and after the changes are the same). [1] CB:83004 [2] CB:83019 Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83196 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/superiotool/superiotool.c M util/superiotool/superiotool.h 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index aee5026..a62f49a 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -84,6 +84,28 @@ return "<unknown>"; } +static void set_extra_selector(uint16_t port, const struct extra_selector *esel) +{ + if (esel->idx == 0) /* entry without extra selector */ + return; + + uint8_t reg_val = regval(port, esel->idx); + reg_val &= ~esel->mask; + reg_val |= esel->val; + regwrite(port, esel->idx, reg_val); + + reg_val = regval(port, esel->idx) & esel->mask; + + printf(" -- ESEL[%02xh] 0x%02x", esel->idx, reg_val); + if (esel->name != NULL) + printf(" (%s)", esel->name); + printf(" --"); + + if (verbose) + printf(" config: idx=%02xh, mask=%02xh, val=%02xh --", esel->idx, esel->mask, + esel->val); +} + static void dump_regs(const struct superio_registers reg_table[], int i, int j, uint16_t port, uint8_t ldn_sel) { @@ -102,6 +124,8 @@ printf("(%s)", reg_table[i].ldn[j].name); } + set_extra_selector(port, &reg_table[i].ldn[j].esel); + idx = reg_table[i].ldn[j].idx; def = reg_table[i].ldn[j].def; diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1409030..ef2bfd6 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -136,6 +136,14 @@ extern int chip_found; +/* Extra selector structure (see fintek.c) */ +struct extra_selector { + const char *name; + uint8_t idx; + uint8_t mask; + uint8_t val; +}; + struct superio_registers { int32_t superio_id; /* Signed, as we need EOT. */ const char *name; /* Super I/O name */ @@ -144,6 +152,7 @@ const char *name; /* LDN name */ int16_t idx[IDXSIZE]; int16_t def[IDXSIZE]; + struct extra_selector esel; } ldn[LDNSIZE]; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/83196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Gerrit-Change-Number: 83196 Gerrit-PatchSet: 9 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de>

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[S] Change in coreboot[main]: mb/google/trulo: support ISH
by Varun Upadhyay (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Deepti Deshatty, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Li1 Feng, Nick Vaccaro, Rishika Raj, Subrata Banik, V Sowmya, Yuval Peress. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83671?usp=email ) Change subject: mb/google/trulo: support ISH ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83671/comment/06f02076_830ffcee?us… : PS2, Line 50: trulo_ish > Acknowledged Let me check internally and come back. File src/mainboard/google/brya/variants/trulo/gpio.c: https://review.coreboot.org/c/coreboot/+/83671/comment/9b227696_2a49eb9d?us… : PS2, Line 147: PAD_CFG_NF > > Acknowledged […] Let me change it to lock config and test. Will update the patch after test. -- To view, visit https://review.coreboot.org/c/coreboot/+/83671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1 Gerrit-Change-Number: 83671 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Yuval Peress <peress(a)google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 14:14:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE
by Jon Murphy (Code Review) 31 Jul '24

31 Jul '24

Jon Murphy has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83680?usp=email ) Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE ...................................................................... soc/intel/adl: Update DCACHE_BSP_STACK_SIZE During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 470dbf4..632798e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -191,12 +191,12 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x80400 + default 0x88000 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement - (~1KiB). + (~32KiB). config FSP_TEMP_RAM_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/83680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Gerrit-Change-Number: 83680 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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